Solid State Drive

Solid-state drives use the parallel access architecture of multi-channel NAND flash memory to provide extremely high read and write performance. At this time, the CPU must have high computing power to cope with high-speed data transmission control, the read and write memory bandwidth of SSD may reach 16GB/s in PCIe 5.0, usually, SSD controller will use a multi-CPU processor architecture for SSD control and NAND flash operations. Furthermore, QoS (Quality of Service), IOPS (Input/Output Operations Per Second), and DWPD (Drive Writes Per Day) all need to have consistent performance and ensure that performance meets high-speed, low-latency, and low-power consumption requirements. To meet the above conditions, Andes provides several 32-bit RISC-V IP cores that not only have leading per-MHz performance, but also have many optional features, such as instruction and data cache, low-latency regional memory, and ECC protection. In addition, Andes Custom Extension™ (ACE) can provide additional flexibility through supporting special purpose custom instructions, so the overall system can achieve a good balance between performance, area, and power consumption. The following provides an overview of the Andes Technology’s CPU solutions suitable for SSD:

AndesCore™ N25F: AndesCore™ N25F is a 32-bit CPU core based on AndeStar™ V5 architecture which incorporated RISC-V technology, it can deliver high per-MHz performance and operating at high frequencies, at the same time it is small in gate count. N25F comes with options, including branch prediction for efficient branch execution, Instruction and Data caches, Local Memories for low-latency accesses, and ECC for L1 memory soft error protection. Features also includes PLIC and vectored interrupts for serving various types of system events, AXI 64-bit or AHB 64/32-bit bus, PowerBrake, QuickNap™ and WFI mode for low power and power management.

AndesCore™ D23: AndesCore™ D23 is a 32-bit 3-stage pipeline CPU core with some dual-issue ability. The D23 implements ePMP and sPMP to improve core security; PPMA for on-the-fly change of memory attributes; and Andes V5 extensions that include StackSafe™ (for hardware stack protection), CoDense™, PowerBrake and WFI/WFE. On the performance front, it deploys several configurable options such as dynamic branch prediction, caches and local memories, multiplier optimized for performance or area.  Moreover, it comes with rich features such as CLIC and PLIC for interrupt handling, an AHB-Lite system bus and an AHB-Lite low-latency interface, an APB bus for CPU local peripherals, and an AHB-Lite local memory access port for external bus masters. 

AndesCore™ N45: AndesCore™ N45 is an 8-stage superscalar processor, it issues two instructions per cycle that significantly increases the performance efficiency. In addition, N45 incorporates MemBoost to greatly enhance memory bandwidth and reduce memory latencies for applications with intensive memory accesses. There are 4 AXI masters for connecting external memories and devices, which can request as non-cacheable or cacheable memory access.  Other features include ECC for memory soft error protection, Platform-Level Interrupt Controller (PLIC) with enhancements for vectored dispatch and priority-based preemption, CoDense™ and StackSafe™ for software quality improvement, PowerBrake and WFI for power management.

AndesCore™ A45MP: AndesCore™ A45MP 32-bit multicore CPU is an 8-stage superscalar processor. It features MMU for Linux based applications, branch prediction for efficient branch execution, level-1 instruction/data caches and local memories for low-latency accesses. The A45MP symmetric multiprocessor supports up to 4 cores and a level-2 cache controller with instruction and data prefetch. It manages level-2 cache coherence including I/O coherence for cacheless bus masters. Other A45MP features include ECC for level-1/2 memory soft error protection, PLIC with enhancements for vectored dispatch and priority-based preemption, CoDense™ and StackSafe™ for software quality improvement, and suspend to standby/memory, CPU HotPlug, PowerBrake, and WFI for power management.

AndesCore™ AX45MP: AndesCore™ AX45MP 64-bit multicore CPU is an 8-stage superscalar processor. It features MMU for Linux based applications, branch prediction for efficient branch execution, level-1 instruction/data caches and local memories for low-latency accesses. The AX45MP symmetric multiprocessor supports up to 8 cores and a level-2 cache controller with instruction and data prefetch. Coherence manger implements MESI protocol to manage level-1 cache coherence, including I/O coherence for cacheless bus masters. Other AX45MP features include ECC for level-1/2 memory soft error protection, Platform-Level Interrupt Controller (PLIC) with enhancements for vectored dispatch and priority-based preemption, CoDense™ and StackSafe™ for software quality improvement, and suspend to standby/memory, CPU HotPlug, PowerBrake, and WFI for power management.