AppoTech Ltd. Selects Andes Technology Corporation N968A CPU For Its Next Generation Audio Codec
AppoTech Ltd. Selects Andes Technology Corporation N968A CPU For Its Next Generation Audio Codec
Andes N968A Superior Performance, Small Code Size, and Audio Extensions
Contributed to Andes Being Chosen Over Rivals
Hsinchu, Taiwan. – July 06, 2017 – Andes Technology Corporation (TWSE: 6533), the leading Asia-based supplier of small, low-power, high performance 32/64-bit embedded CPU cores, today announced that Hong-Kong-based AppoTech Ltd., the 2016 China Ministry of Industry CSIP “Best Market Performance Product Award” winner, has selected Andes N968A for a next generation audio codec SoC. Andes N968A’s superior performance, compact code size resulting from the ability of the CPU to intermix both 32-bit and 16-bit instructions contributed to AppoTech’s choice of Andes over competitive alternatives. Also attractive to AppoTech was the N968A’s Audio extensions and data local memory feature that speeds memory accessed.
CEO and President of AppoTech Ltd., Chuck Cheng stated, “Andes has provided us with an efficient CPU core for our next generation SoC. AppoTech has targeted the rapidly growing China market and we need partners like Andes to help provide a technical edge in this highly competitive arena. To enhance our competitiveness, we needed to move away from discrete logic design of our codecs to one based on a programmable processor that could easily accommodate a variety of different audio coding algorithms. Andes CPU core provided us this flexibility, while giving us an advantage of high compute performance in a small die size.”
“We are very gratified that AppoTech selected Andes for its next SoC design,” said Andes President, Frankwell Jyh-Ming Lin. “Having AppoTech—a market leader in video, audio, telecommunications, home entertainment, car music systems, and other vertical markets—select Andes is a great vote for our leadership in high-performance low-power CPU IP technology. Our engineering team has worked hard to build efficient Audio acceleration functionality into the N968A that makes it ideal for performing efficient computations audio codecs demand.”
With the most versatile Audio instructions, the N968A can perform two parallel loads from two memory banks plus an independent multiply-shift-accumulate. The powerful Audio instructions allow designers to implement an audio codec platform in software to achieve great efficiency while providing flexibility unmatched by hardwired solutions. The compact and fast code generated by Andes open-source GNU toolchain, easy-to-use AndeSight™ IDE and RTOS support enable customers such as AppoTech to rapidly develop versatile applications with high quality for their final chip.
About AppoTech
AppoTech Ltd is a fabless IC company that designs high performance, high reliability and cost-effective system-on-chip (SoC) products. The company offers a complete solution from IC design to application development for applications including video, audio, telecommunications, consumer electronics and home appliances. It is based in the IC Development Center, No.6 Science Park West Avenue, Hong Kong Science Park, Sha Tin, Hong Kong.
After 15 years in the Silicon Valley at National Semiconductor and Sun Microsystems among others, founder and CEO Chuck Cheng formed the company in 2003 in Palo Alto California with ten employees and $1 Million of his own money. Attracted by the generous government incentives, such as subsidized rent in a new science and technology park, and strong intellectual-property laws, he moved the company to Hong Kong. There the company is a day trip from mainland China’s Pearl River Delta, the world’s factory for everything electronic.
The company has grown since its founding to become a major supplier of SoC solutions in rapidly growing markets such as consumer electronics. In November 2016, the latest generation of its SoC Bluetooth chip won China’s Ministry of Industry and the Ministry of Industry CSIP “Best Market Performance Product Award.” In December 2015, the company and its CEO won the 2015 Hong Kong Award for Industry and Commerce (Science and Technology Achievement Award) at the Hong Kong Convention and Exhibition Center. The company’s ultimate goal is to become the world’s leading integrated circuit design enterprise.
About Andes
Andes Technology Corporation was founded in Hsinchu Science Park, Taiwan in 2005 to develop innovative high-performance/low-power 32/64-bit processor cores and associated development environment to serve worldwide rapidly growing embedded system applications. The company delivers the best super low power CPU cores with integrated development environment and associated software and hardware solutions for efficient SoC design.
To meet the demanding requirements of today’s electronic devices, Andes Technology delivers configurable software/hardware IP and scalable platforms to respond to customers’ needs for quality products and faster time-to-market. Andes Technology’s comprehensive CPU includes entry-level, mid-range, high-end, extensible and security families to address the full range of embedded electronics products, especially for connected, smart and green applications.
For more information about Andes Technology, please visit http://www.andestech.com/.
Andes Technology Provides System Control Processor IP for Wave Computing’s Revolutionary Dataflow Processing Unit Design
Andes Technology Provides System Control Processor IP for Wave Computing’s Revolutionary Dataflow Processing Unit Design
Hsinchu, Taiwan. – June 19, 2017 – Andes Technology Corporation (TWSE: 6533), the leading Asia-based supplier of small, low-power, high performance embedded CPU IP, today announced that Wave Computing’s revolutionary Dataflow Processor Unit (DPU) chip leverages Andes system control processor IP in its current generation design. Andes processor IP, bus fabric, peripheral IP, and complete open software development environment provided Wave’s design team a complete drop-in solution that reduced verification effort and cost.
“Building a leading-edge 6.7 GHz design at 16 nanometer with 16,000 processors demands an engineering team’s complete commitment and focus,” said Darren Jones, Vice President of Hardware Engineering at Wave Computing. “Andes drop-in solution and related software enabled us to easily integrate a complete system control subsystem into our SOC.”
“We are thrilled that Wave Computing, an existing customer, used Andes IP in its industry leading deep-learning DPU design,” said Charlie Hong-Men Su, Ph.D., Andes Technology CTO and Senior Vice President of R&D. “Andes IP provided Wave with a complete drop-in solution that can be programmed in software to perform housekeeping functions such as boot code loading, sequencing the power-up of the chip, and monitoring the heat profile of the chip as it carries out its tasks. And our feature-rich AndeSight Eclipse-based integrated software development environment provided Wave an efficient way to develop embedded applications for their Andes system controller IP with small code size and high performance.”
About Andes Technology Corporation
Andes Technology Corporation was founded in Hsinchu Science Park, Taiwan in 2005 to develop innovative high-performance/low-power 32/64-bit processor cores and associated development environment to serve worldwide rapidly growing embedded system applications. The company delivers the best super low power CPU cores with integrated development environment and associated software and hardware solutions for efficient SoC design.
To meet the demanding requirements of today’s electronic devices, Andes Technology delivers configurable software/hardware IP and scalable platforms to respond to customers’ needs for quality products and faster time-to-market. Andes Technology’s comprehensive CPU includes entry-level, mid-range, high-end, extensible and security families to address the full range of embedded electronics products, especially for connected, smart and green applications.
For more information about Andes Technology, please visit http://www.andestech.com/.
Andes Technology and M31 Technology Collaborated on Optimal Power Efficiency CPU Implementation for IoT SoC Market
The AndesCore™ N705 is a 32-bit low-power small-gate-count CPU IP core, a member of AndesCore™ processor families from Andes Technology. Designed with the AndeStar™ V3m architecture and a 2-stage pipeline, N705’s dynamic power consumption is less than 60% and its power efficiency is more than two times of same class of product on the market. It also supports features like PowerBrake and FlashFetch™ for additional power managment and performance improvement.
Under this cooperation, M31 provides further low-power IP solutions in 40 nm process technology. These IPs including “Low Power Cell Library” and “Green Memory Compiler” for Andes N705 CPU at the physical implementation level:
•Low Power Cell Library, which includes the Standard Cell Library, the unique Low Power Optimization Kit, and the Power Management Kit (PMK).
•Green Memory Compiler, with “dual-rail memory operation” to help customers with “Dynamic Voltage Frequency Scaling (DVFS); with “Power Gating Technology” to handle the “Static Leakage Power Consumption” in different operating modes.
“AndesCore™ N705 is well suited for SoC designs on IoT, biomedical, wearable and intelligent home appliances because its architecture was specifically designed to deliver high performance at very low power consumption.” said Dr. Charlie Su, Andes Technology CTO and Senior Vice President of R&D. “With M31’s low-power IP solution and Power Management Kit, it is able to reduce static power consumption by 50% from Clock-Gating mode to State Retention mode, and to reduce additional 75% from State Retention mode to Power-gating mode.”
“Together, the Power Management modes, the Dynamic Voltage and Frequency Scaling (DVFS), the Low Power Cell Libraries and Memories, and N705’s power efficient architecture make possible this impressive advancement for ultra-low power processor implementation,” he said. “As the requirements for the standby time and the operating time are ever-increasing in each new generation of battery-powered devices, we will continue cooperating on the low power technologies to provide comprehensive solutions for the industry.”
Willis Shih, RD VP of M31 Technology, stated, “M31 is very glad to cooperate again with Andes Technology. M31’s low-power silicon IPs and Power Management Kit (PMK) provide a total solution for SoC design whether on dynamic power consumption or on static power consumption. These low power consumption features are particularly applicable for the IoT and wearable products market; helping enhancing customer competency and to satisfying the overall design requirements on IoT applications, such as low power consumption, low cost, and power management goals. In the future, M31 will continue its IP development and validation in advanced process technologies to provide distinctive silicon IP to the worldwide chip design community. These IP solutions will satisfy customer SoC design on various low voltage supply and low power consumption, in order to help customers grasp market opportunities through short design cycles, low manufacturing cost, and high product competitiveness.”
About M31 Technology
M31 Technology Corporation is a professional silicon intellectual property (IP) provider. The company was founded in July, 2011 with its headquarters in Hsinchu, Taiwan. M31’s strength is in R&D and customer service. With substantial experiences in IP development, IC design and electronic design automation fields, M31 focuses on providing high-speed interface IP, memory compilers, standard cell library and ESD/IO library solutions. For more information please visit www.m31tech.com
For more information about Andes technology and its low power, high performance AndesCore™ Processor IPs, please refer to www.andestech.com or contact sales@andestech.com
For more about M31 low-power IP solution and PMK kit, please visit www.m31tech.com or contact sales@m31tech.com
Andes Technology Corporation the First Mainstream CPU IP Provider to Adopt RISC-V Expands Product Lineup to offer 64bit Processor IP
Complete Solution Builds on the Customer-Proven AndesStar™ Infrastructure to Reduce Time to Market and Design Risk for Companies Seeking 64-bit SOC Solutions
San Jose, California. – May 9, 2017 – Andes Technology Corporation, the leading Asia-based supplier of high performance, low-power, small embedded CPU cores serving 2-billion SoCs, today announced a new generation of the AndeStar™ architecture. In the process, Andes becomes the first mainstream CPU IP provider to adopt RISC-V, the open RISC Instruction Set Architecture (ISA) developed at the University of California Berkeley. Andes ISA, called AndeStar™ V5, supports 64-bits and the widely known RISC-V ISA as its subset and will bring the open, compact, and modular RISC-V into mainstream SoC applications. The AndeStar infrastructure, evolved over the past 12 years includes advanced features such as CoDense™, PowerBrake, and StackSafe™, and application-specific architecture extensions such as Custom Extensions, DSP Extensions and Security Extensions, in addition to strong compiler optimizations for the optimal performance and code size. Adding 64-bit capabilities to Andes existing families of IP cores will satisfy new SoC’s requirement for addressing memory over 4GB in applications such as high capacity storages, large-scale networks, deep learning and AI systems. Leveraging Andes’ history of industry leading performance-to-power ratio, SoCs with AndeStar™ V5 based cores will be able to run efficiently at high frequency. For example, the new V5 AndesCore™ NX25 in a typical configuration will deliver over 1GHz (in “worst case” conditions) with area of only 67K gates and with power consumption as little as 17 µW/MHz in a TSMC 28nm process.
“Time-to-market is a major concern in every SoC design and one task that slows design progress is writing RTL code simply to integrate a collection of standard IP blocks and then spending an equal or greater amount of time verifying the new code” said Charlie Hong-Men Su, Ph.D., Andes Technology CTO and Senior Vice President of R&D. “With the new AndeStar™ V5 architecture, we provide a complete solution for 64-bit embedded SoC designs by bringing RISC-V compliance together with Andes’ successful line of AndeStar™ V3 IP cores, convenient features (such as CoDense, PowerBrake and StackSafe) and architecture extensions (such as Custom Extensions, DSP Extensions and Security Extensions), standard Andes IDE software toolchain with comprehensive extended features, SoC peripherals, hardware developing platforms, service and support. Collectively, this helps to satisfy needs of design teams by significantly improving the product quality and reducing time-to-market and risk for production-ready 64-bit SoC designs. When Andes started to plan AndeStar™ V5, we considered the full scope of supporting an extended ISA, enabling customers to leverage fertile RISC-V ecosystem while maintaining the strengths we accumulated over time.”
Differentiation of AndeStar™ V5 Solution
Andes is the first mainstream CPU IP provider to adopt RISC-V. The AndeStar™ V5 architecture is fully compliant with RISC-V while bringing extended (superset) features unique to Andes and providing full support of the AndeSight IDE development tools. This approach offers customers a way to develop 64-bit software in the same convenient environment as in V3. In addition, the powerful Andes Custom Extension™ (ACE) environment greatly simplifies the task of extending application-accelerating instructions for V5 by automatically generating all necessary development tools and housekeeping RTL code, and automatically verifying custom logic against its defined behavior. Furthermore, products based on AndeStar™ V5 will support the extensive line of silicon-proven Andes SoC peripherals including the Andes System Control Platform and have the benefit of Andes extensive validation for use with industry-standard EDA tool and libraries. Furthermore, AndeStar™ V5 provides support for addressability of greater than 4GB, AXI 64-bit interface, GCC compiler and GDB debugger which had being validated by strict industrial and Open Source test suites. Therefore AndeStar™ V5 is the comprehensive solution for customers to achieve optimum performance for their products and to shorten their development cycle.
Availability
AndeStar™ V5 is available now, the first AndesCore™ based on AndeStar™ V5 – called the NX25 – will be available the third quarter of this year. Also available will be the AndeSight™ IDE that supports integrated development environment for AndeStar™ V5-based SoC, pre-integrated System Control Processor platform with a configurable interrupt controller with up to 1023 interrupt sources, Andes ADP-XC7 FPGA development board, and Andes High-value Service and Support.
For more information, e-mail info@andestech.com.
- Go to the previous page
- 1
- …
- 10
- 11
- 12
- 13
- 14
- 15
- 16
- …
- 24
- Go to the next page
