Andes Technology Unveils New Low-Power Platform IP Ideal for Internet-of-Things, Wearable Devices and other Power-Sensitive Applications

【HsinChu Taiwan】Andes Technology (www.andestech.com), Asia’s first dedicated vendor of 32-bit CPU cores and associated System-on-Chip (SoC) platforms, unveiled a new low-power SoC subsystem for expanding Internet-of-Things (IoT) and wearable device markets. Called the AndeShape™ AE210P, this configurable and highly efficient IP, can be easily integrated with any AndesCore™ or those from other IP vendors and is ideally suited for a variety of popular MCU applications where power considerations are critical. These include: smart sensor devices, medical devices, intelligent appliances, touch panels, wireless charging and power management ICs.

“Power efficiency is critical for many emerging applications,” commented Rich Wawrzyniak, Senior Market Analyst with Semico Research. “More and more SOCs are being designed with subsystems that solve a larger part of the design challenge. By introducing a lower-power solution, Andes is servicing an increasingly important market need.”

The AE210P provides flexible and diverse configurations, giving customers the options to select and tune peripheral IPs for meeting their unique design requirements. For example, if cost is the highest consideration, designers can choose the simplified bus structure of a single APB to support basic peripheral IPs, with a gate count as low as 11K. When pursuing the optimum performance and the best throughput, they can have an AHB bus matrix plus the APB bus. In terms of peripheral IPs, the AE210P allows versatile combination from DMA controller, PWM, watchdog timer, Real Time Clock (RTC), UART controller, SPI controller, I2C Controller and bus controllers for AHB master/slave and APB. These bus controllers, bridge controllers and peripheral IPs are all designed to maximize the system performance and minimize the access latency, logic gate count, power consumption and cost. With the AE210P already silicon-proven, customers can confidently integrate their modules through the provided interfaces and focus on their part of the designs. This also dramatically boosts the efficiency and quality in product development and shortens time-to-market.

“32-bit MCU products are penetrating the consumer market at a frantic pace,” remarked Dr. Charlie Su, Chief Technical Officer and Senior VP of R&D at Andes. “The AE210P provides a pre-verified and pre-integrated platform IP that contains common functions required for many MCU applications – with reduced power. Using the standard TSMC 90nm LP library, the AE210P can deliver frequencies up to 200 MHz for high-performance applications, while power consumption can be as little as 98uW (82uA) for low power mode. This makes it an ideal platform for IoT and wearable devices that demand ultra-low-power consumption for long battery life. The AE210P also enables customers to meet efficiency requirements and speed up their development process. These benefits are easily demonstrated by its access acceleration for NOR Flash, a typical memory among various MCU applications. It not only offers Serial Peripheral Interface (SPI) for direct program execution from Serial Flash, but also employs the FlashFetch™ technology to accelerate the access time from Parallel Flash.”

Dr. Su further states, “Using the AE210P, customers can complete their SoC designs with ease by integrating their modules with the platform, greatly shortening the development time. For developers with strong needs for SoC optimization, the AE210P also allows configuration for respective peripheral IP. Such flexibility provides significant benefits for companies moving from 8- or 16-bit MCUs to 32-bit MCUs. The combination of the AE210P with AndesCore™ CPU IPs is fully supported by the AndeSight™ IDE and BSP components like toolchains, demo applications and real-time operating systems such as FreeRTOS, ThreadX, and uc/OS-II. As a softcore platform, the AE210P fits in any semiconductor manufacturing processes. Andes also provides an FPGA development board for performance evaluation and software development too. All in all, the AE210P plays a key role in Andes’ 32-bit MCU total solution covering hardware, software and two-wire ICE debugger. For suppliers of MCU applications and system manufacturers, it is integral to create competitive products with optimum performance and reduced cost.”

“Our ThreadX RTOS is an ideal match for the power-conscious AE210P, with our small memory footprint and highly efficient code,” commented William E. Lamie, President of Express Logic, Inc. “ThreadX is used in over 2 billion electronic products in the areas of consumer electronics, medical devices, and industrial control equipment. ThreadX supports IoT development for wearable and portable devices based on the AE210P, that require efficient, high-performance, and easy-to-use operation.”

For more details about Andes 32-bit CPU IPs, please visit www.andestech.com.

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AndesCore™ N968A: the Optimal Choice for Developers in Pursuit of High Performance and Low Power Consumption

【Taiwan HsinChu】As 32-bit MCU devices are sprouting in the consumer electronic market, suppliers keep pursuing higher integration and greater energy saving while speeding up the release of new products. Following this trend, Andes Technology Corporation, Asia’s first dedicated vendor of innovative 32-bit CPU IPs and associated SoC platforms, launches the AndesCore™ N968A IP core. This licensable solution is tailored for MCU applications that demand a combination of high performance and low power consumption. With its outstanding performance, the N968A has already been embedded in SoCs for high volume fields like touch panel control, three-phase motor control, mobile health devices, computer peripherals, white goods, personal care devices, handheld devices and wireless networking.  

The N968A delivers an impressive performance of 1.92 DMIPS/MHz with dynamic power consumption of only 31.7 uW/MHz. With the resulting power efficiency of 60.6 DMIPS/mW, the N968A provides significant benefits for developing low-power, high performance SoCs. By employing breakthrough technologies such as hardware configurability and the latest AndeStar™ V3 instruction set architecture, chip vendors get rich peripheral integration and superior efficiency while minimizing cost. Using Andes’ novel V3 architecture, the N968A achieves optimum system efficiency with minimum code size and power consumption. Moreover, the N968A features advanced power management capabilities and incorporates rich bus interface for either AHB or  AXI, meeting the control requirements of next-generation applications.

Dr. Charlie Su, Chief Technical Officer and Senior VP of R&D at Andes, states, “Whether using Flash or ROM the instruction memory on typical MCU-based chips often consumes at least twice the size of processor. Thus it is memory that typically dictates the size – and the cost – of MCU-based chips. The N968A dramatically reduces the instruction memory size and cost through higher code density, especially when compared to legacy 8- or 16-bit MCUs. By combining exceptional performance with very low power consumption, the N968A delivers excellent power efficiency, outperforming 8-bit MCUs by at least three times and offering more than 40% efficiency boost over the competing 32-bit MCUs. For chip designs which used to adopt 8 or 16-bit MCUs, the 32-bit N968A provides a seamlessly update and makes a great improvement in all aspects. Andes’ N968A is a must-have to create competitive products with low cost and high efficiency.”

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Andes Custom Extension™ (ACE) Enables Andes Processors to Provide Acceleration for Specific Applications

【Taiwan HsinChu】 Andes Technology, the first dedicated vendor of innovative 32-bit CPU IPs and associated SoC platforms in Asia, announces its brand new SoC development solution, the Andes Custom Extension™ (ACE) framework, and the first supporting AndesCore™ processor, the EN801. With the easy-to-use ACE language, customers can create instructions specific to their applications and optimize the performance and power consumption in a much shorter timeframe. The programmability allows more performance efficiency on a chip and provides protection for proprietary software IPs through custom instructions. The ACE framework can be used from DSP acceleration and high-volume data processing to emerging applications whose features and specifications are still evolving such as IoT, wearable devices, smart sensor devices, medical devices, storages, packet processing, intelligent household appliances, touch panels, wireless charging, fingerprint identification, SSD and encryption security chips.

Supported by the ACE framework, the EN801 is the first extensible AndesCore™. Designers can create application-specific instructions to meet the most stringent product requirements with high performance efficiency. The resulting programmable acceleration allows a single chip to offer more functionalities than those relying on hardwired engines. Here are a couple examples,

  • A MADD operation with two 16×16 bit multiplication added to 32 bits has 8 times speedup.
  • A FIR filter with 64 bits of precision achieves 17 times speedup.
  • A 32-bit CRC32 operation delivers over 90 times speedup. 


Under the ACE framework are the ACE language and COPILOT tool (Custom-OPtimized Instruction deveLOpment Tools™) to simplify the instruction design process. Based on ACE descriptions, COPILOT generates the corresponding extended RTL, verification environment and relevant extension modules to be used with Andes standard development tools, simulator and AndesCore RTL. For SoC developers who need programmability and efficiency, ACE directly addresses their needs. As ACE gives the extensibility for developers to add application-specific instructions, it also offers post-silicon programmability to modify or extend functionalities. This facilitates the re-engineering of products without the trouble of starting a new SoC design process for different product positioning – which is a compelling advantage over SoCs with excessive hardwired functions. 

Dr. Charlie Su, Chief Technical Officer and Senior VP of R&D at Andes, states, “The launch of the ACE framework responds to our customers’ increasing demands for extensible processors after they encounter all sorts of problems during SoC development. They are not satisfied with traditional extensible processors using complicated tools restricted to high-end applications and the early-stage baseline CPU cores in these processors. Some existing extensible processors don’t even come with any baseline CPU core, forcing customers to develop one themselves. Foreseeing the trend of new generation extensible processors with the rise of intelligent devices, Andes introduces the EN801 which is supported by the ACE framework and inherits high efficiency, low power consumption and compact code size from the highly-optimized AndesCore N801. The extensible processor EN801 allows SoC developers to incorporate functionalities and increase flexibility for SoC optimization. Through the ACE language and COPILOT, SoC developers can define their own instructions with ease and simplify the design process of extending RTL and simulator, thereby facilitating the instruction creation while avoiding tedious and error-prone design work. In an era of ever-changing applications and product requirements, Andes is ready to take on more performance and power consumption challenges with the ACE framework.”

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Andes Technology and M31 Technology Cooperate in Building UP Optimized CPU Solution

【Hsinchu, Taiwan】June 30, 2014 – Andes Technology Corporation (www.andestech.com), the first and leading supplier of licensable processor cores in Asia, and M31 Technology, the boutique Intellectual Property provider, today announced together that AndesCore™ N1337 has adopted M31’s advanced technology MACH™ to reach 1GHz frequency under 40nm process. N1337 as a high speed CPU solution can be applied to handheld devices, intellignet TV, tele-communication, and consumer entertainment applications.

Embedded with Andes’ 32-bit microprocessor core AndesCore™ N1337, SoC can obtain innovative advantages of low power, small area, high performance, and be benefited from its easy-to-use flexible development platform. The major target applications are controller SoC for DTV, Digital Home, Setop Box, Switcher, Router, Fiber Network, Surveillance, SSD, ADAS, etc.

Andes’ CTO and R&D VP Dr. Charlie Su stated “AndesCore™ N1337 implemented by Andes’ newest V3 instruction set and equipped with saturation instructions, is an 8 pipeline stage, 32-bit processor which can reach as high as 1.87DMIPS/MHz. N1337 supports 64-bit AXI in addition to popular AHB bus. Its innovative architecture ensures to meet the most demanding SoC efficiency requirement. In addition, N1337 supports common interface allowing instruction fetch, data access and DMA to simultaneously access Unified Local Memory (ULM), which tremendously increases data transmission speed and is very suitable for large amount of data handling in a RTOS system. For Linux support, N1337 implements Memory Management Unit (MMU) and L2 Cache. With Andes’ L2 Cache controller, N1337 can be applied to high end applications.”

MACH™ family of M31 Technology includes three essential components to speed up CPU frequency. Its ultra-high-speed (UHS) memory complier is designed to meet the critical performance requirement of CPU L1 cache. MACH™ cell library is to boost the performance of CPU logic. And, MACH™ optimization flow with unique numerical algorithms can dynamically adjust the transistor sizes and create new cells to reach optimal performance.

Mr. H.P. Lin, M31 Technology’s Chairman, stated “M31 is very glad to become a partner of Andes Technology. M31’s MACH™ family can analyze customer’s cell library to give dynamic adjustment and create new cells. MACH™ family provides customers various solutions for high speed interface applications including CPU and GPU market.”

Mr. Frankwell Jyh-Ming Lin, Andes Technology’s President, stated “CPU performance is the most challenging goal of portable devices including cell phones and tablets. Adopting M31’s MACH™ family can speed up 10%~15% performance. Andes Technology is very glad to cooperate with M31 and appreciates the co-development opportunity. M31 has become another powerful technology partner for Andes. Andes’ 32-bit processor cores and development tools have been widely adopted in this industry with positive reputation. Andes will continuously develop products in diversified segments for different applications, and hopes to bring Andes’ customers the best technology, service and solutions.”

For more information about Andes technology and its low power, high performance 32-bit CPU IP series, please refer to www.andestech.com or contact  sales@andestech.com.

 

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Andes Targets Sensor SoCs with its Ultra Power-Efficient Processor Core

【Taiwan HsinChu】“The total number of sensor units is estimated to grow from just under 10 billion in 2012 to nearly 30 billion in 2017,” said Tony Massimini, chief of technology at Semico Research. Noticing the soaring trend of sensor-based applications, Andes Technology Corporation, the first dedicated vendor of innovative 32-bit CPU IPs and associated SoC platforms in Asia, drives its ultra energy-efficient, cost-effective 32-bit processor AndesCore™ N705 to the emerging market. Announced last April in Andes-Embedded Forum, the N705 is an achievement of Andes’ 8-years research. It delivers 141 DMIPS/mw at 90nm low power process, which outperforms competing products from other industry-leading vendors by 30%. Code named “Hummingbird,” the N705 is geared towards light-weight and low-power products. Featuring ultra power-efficiency, compact gate count and the exclusive FlashFetch™ technology, the N705 caters to all sorts of sensor-based applications including smart sensors and sensor hubs.

The N705 provides Instruction/Data Local Memory interface option that allows direct connection to memory. In addition to AHB-lite, it directly incorporates APB bus interface for lower-speed devices. These characteristics effectively reduce the cost of sensor SoCs, speed the development and integration flow, and enable faster time-to-market. While applications like the IoT (Internet of Things), automobiles, and mobile devices are demanding more abilities to capture and interpret environmental conditions (pressure, temperature, motion, proximity and more), the N705 with the built-in 32-bit multiplier and divider accelerates the complex calculation required for sensor fusion algorithm. Using the latest AndeStar™ V3m architecture, it also significantly reduces code size.

The AndesCore N705 is a 32-bit general purpose embedded processor that demonstrates extreme power-efficiency. For ease of integration in SoC design, it is delivered with a reference design flow to meet diversified requirements in performance, power consumption and die area. In addition, it also comes with a complete software development package including the all-C Embedded Programming environment, C libraries optimized for MCUs and 2-wire low-cost ICE debugger. In its minimum configuration, the N705 achieves the leading-edge energy efficiency of 141 DMIPS/mWatt at the 90nm low power process with only 12K gates. Reaching up to 1.51 DMIPS/MHz and 2.62 CoreMark/MHz, the N705 stands out among 32-bit embedded CPUs of the similar complexity.

Jyh-Ming Frankwell Lin, President of Andes Technology Corporation, said, “As sensors are getting ubiquitous, applications in this era must have a compact size and deliver high performance with low power consumption. The AndesCore N705 offers competitive power-efficiency, low gate count and rich interfaces, making it ideal for the design of sensor fusion SoCs. Moreover, it can be connected to the low-speed and power-hungry flash memory directly. Utilizing the FlashFetch™ technology, the N705 is capable to run at its full speed without being hindered by the flash memory and meanwhile reduces over 50% flash power consumption in EEMBC’s CoreMark® benchmark. By all means the optimal choice for developers, the N705 together with the comprehensive software support is ready to take sensor-based applications to the next level.”

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The 9th Andes-Embedded Forum (AEF-9) Takes Place in Hsinchu and Shanghai

Andes Technology Corporation’s 9th Embedded Forum (AEF-9) focusing on IoT and Wearable Solution was successfully held in Hsinchu, Taiwan on May 22 and in Shanghai, China on May 29. Andes President Frankwell Lin gave a keynote speech about Andes’ achievements and progress over the past whole year and expressed deep appreciation to Andes’ partners and customers for their support. Dan Kochpatcharin, Deputy Director of IP Portfolio Marketing at TSMC, also gave a speech on “Smart Connected Life” for the opening. A series of speeches surrounding IoT and Wearables followed then successively to demonstrates Andes’ strength for the emerging IoT/Wearable era. These speeches included “IoT and Wearable Applications Evolution and Outlook,” “Extending Beyond Today’s Performance Horizon Through Andes Customer Extension™,” “Building Low-Power SoC for IoT and Wearable Computing Through Andes Processor/Platform Solutions,” “Andes Software Solutions for Smart Connected Devices,” “32-bit MCU for NFC Reader Applications,” “Development of Smart Wearable Devices” and “Relationship between CES 2014 and Andes Service.” Together with the Q&A session and Andes’ partner/customer exhibitions, the AEF-9 enabled participants to share techniques and exchange experiences in shaping the IoT/Wearable world.

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Andes Wins Over Large Publicly Traded Company as Newcomer to Japanese Market

【Taiwan HsinChu】Even with the slow recovery of global economy in 2013, the demand of semiconductor business in Japan is projected to see a healthy growth of 5.8% to reach $43.4 billion, according to a report from Industry & Technology Intelligence Service (ITIS). Playing a significant role in the semiconductor industry, Japan is a target market that Andes Technology won’t miss when considering going global. After steady efforts to promote AndesCore™, Andes scored its first win in Japan this August by licensing N705-S to a vendor of electrical/electronic equipments. The licensee is a large Japanese publicly traded company with annual revenue of over $2 billion and focuses on the production of temperature controllers, flow control instruments and heat treatment controllers. Andes stands out among competitors, including the one with the largest CPU IP market share, for the superiority of AndesCore™ CPUs in terms of power, performance, and area (PPA). In addition, the licensee is impressed with Andes’ comprehensive development tools and RTOS support. Furthermore, Andes offers prompt and efficient customer support that fully matches high quality standards of the Japanese company.

Andes has started expanding its business to Japan since last year. Its brand yet remains relatively unknown in the country, despite the good reputation and market share in Taiwan, China and Korea. Therefore, in addition to signing contract with the large publicly traded company, Andes also undertakes several marketing activities in Japan. Recent ones are the participation in GSA Semiconductor Leader Forum (Tokyo, October 29th) and Embedded Technology Conferences & Exhibition (Yokohama, November 20th). Through these activities, Andes expects to create awareness of Andes CPU cores and generate more customers in Japan.

Jyh-Ming Frankwell Lin, President of Andes Technology Corporation, stated, “To provide potential customers in Japan with a variety of choices, in the short term, Andes plans to introduce higher-end processors, such as N9, N10 and N13, along with the promotion of N705-S. While Andes also enters the final evaluation stage of another Japanese company now, we believe that our strengths in ultra low power through performance efficiency, small die size and solutions to address SoC issues will be recognized by more and more companies here. In the long run, Andes will reinforce ties with customers by attending international conferences and organizing forums. An upcoming in-depth book about Andes CPU cores by Munetomo Maruyama (32-Bit CPU Core Developed in Taiwan: AndesCore, CQ publishing) is also expected to seize the interests of electrical/electronic system manufacturers, IC design houses and IDMs in Japan. We look forward to the rapid growth of Andes licensees here in the near future.”For more information about Andes Technology and AndesCore™, Andes high-performance/low-power 32-bit processor cores, please referto www.andestech.com or contact sales@andestech.com.

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Andes Exhibits at TSMC 2014 NA Technology Symposium Ecosystem Pavilion

Andes Technology exhibited at the TSMC 2014 NA Technology Symposium Ecosystem Pavilion, San Jose McEnery Convention Center, California, on April 22. Participating with other TSMC OIP (Open Innovation Platform) ecosystem member companies, Andes as an IP partner introduced its high performance, low power 32-bit processor core families with SoC development environment to attendees and showcased AndesCore™-embedded applications which have been in mass production. In the exhibition, booth visitors were impressed with Andes’ competitive CPU IPs and robust platform solutions while exchanging information with Andes US staff. Andes also demonstrated in the event that it’s ready to get deeper and broader involvement in the design ecosystem with its most advanced CPU IP technology.
 

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