Andes Technology Launched AndeStar™ V3
a New-Generation Smart Low-Power 16-/32-bit Mixable Instruction Set Architecture (ISA), to Reduce IC Cost, Improve Efficiency, Facilitate Development and Shorten Time-to-Market
【Taiwan HsinChu】For years, Andes Technology has been dedicated to developing CPUs and platforms that deliver easy integration, scalability, and design flexibility. To cater to demands of IC design companies and OEMs, it also offers comprehensive product lines and feature-rich development tools. Recently in its 7th Andes-Embedded™ Forum, Andes Technology announced the launch of AndeStar™ V3, a new-generation, smart, low-power Instruction Set Architecture (ISA). AndeStar™ V3 is 16-/32-bit mixable ISA and backward-compatible to V2 ISA. It minimizes executable code size to allow customers to adopt smaller-sized memory to reduce IC cost or put more features in the same-sized memory. In terms of MCU benchmarks, AndeStar™ V3 demonstrates executable code size reduction of over 20% on average when the size of the V3 code is compared to that of the preceding V2 code. With the introduction of All-C Embedded Programming development environment, AndeStar™ V3 enhances the performance of interrupt handlers and improves debugging capabilities, thereby significantly shortening product development cycle and time-to-market for customers.
The applications of AndeStar™ V3 are extensive, including networking, DTV, Digital Home, DSC, DVD, game consoles, PC peripherals, storage, smart meters, industrial control, automobiles, medical devices, and various communication protocols such as Bluetooth and WiFi. AndeStar™ V3’s features and functionalities serve to raise the competitiveness of these product applications in the global market.
Dr. Chuan-hua Chang, Director of Architecture Division at Andes, stated, “V3-based CPUs can run V2’s executable code as AndeStar™ V3 is backward-compatible. After upgrading their CPU cores to V3-based CPUs, existing V2-based CPU customers do not have to modify or recompile their programs in a hurry. However, they can benefit fully from the features of V3 ISA by recompiling their programs. The V3 program development toolchain will use special instructions to reduce repeated instructions, replace frequently-used instruction sequences with fewer instructions, and use shorter instructions to handle common tasks of functions. These features all bring effective boosts to code density.”
Dr. Chuan-hua Chang further explained, “AndeStar™ V3 offers compiler support for hardware architecture. That is, it provides a development environment of All-C Embedded Programming for developers to write all their code in C and save the trouble of using assembly language. As to interrupt service routines, AndeStar™ V3 adopts priority-based preemptive interrupt scheme. CPU will handle an interrupt request with the highest priority first, thus speeding up the handling of higher priority interrupts and increasing overall efficiency. Moreover, AndeStar™ V3 also improves debugging capabilities, enabling early discovery of problems that are not very obvious. – With all these features, AndeStar™ V3 not only accelerates time-to-market but also greatly reduces development time, revision, and maintenance overhead.”
Please contact sales@andestech.com for more information about AndeStar™ V3, the new-generation smart low-power backward-compatible 16-/32-bit mixable Instruction Set Architecture.
Andes Technology Launched AndesCore™ SN801, the New Generation Processor Core with Security Features.
With High Power-Efficiency and Side Channel Attack Prevention, SN801 Becomes the Best Choice for SoC Developers when Designing Lightweight and Low-power Secure Products.
【Taiwan HsinChu】For new-generation SoC design, delivering 32-bit features and performance along with 8/16-bit cost is a must if one wants to stand out in a competitive market. To meet these requirements, Andes Technology launched the latest-generation AndesCore™ SN801, a 32-bit CPU with advanced security features, in its recent 7th Andes-Embedded™ Forum. SN801 is based on the energy-efficient N801 processor core and designed with secure MPU (Memory Protection Unit). It not only adopts a comprehensive protocol to manage privilege levels but also provides hardware mechanisms for code and data protection. Effectively preventing side channel attacks, AndesCore™ SN801 processor core is the best choice for SoC developers to design lightweight and low-power secure products.
AndesCore™ SN8 series combines streamlined 3-stage pipeline with protective instruction set architecture. With its complete and robust architecture, SN801 enables customers to assign security levels by setting passwords or implement tamper-proof mechanisms according to application needs. The applications of SN801 cover from emerging NFC, bank cards, medical insurance cards, memory cards to e-passports and more. By migrating to SN801 that significantly surpasses legacy 8/16-bit processors, IC design companies can hammer out low-cost, low-power, highly secure and competitive products to address ever-renewing and fast-growing applications.
Dr. Charlie Su, Chief Technical Officer and VP of R&D at Andes, states, “According to a market research report, the global shipments of smart cards are expected to reach around 8.5 billion units by 2013. Specifically targeting applications pertaining to smart cards, AndesCore™ SN801 accelerates the associated SoC design and development, reduces the time for product certification and speeds the entry to market, thereby benefiting customers to vie for share of the ten-billion-unit smart card market. AndesCore™ SN801 fully caters to the demand of new generation SoC design with its 32-bit features and 8/16-bit cost advantage, making it the optimal choice for SoC developers when designing lightweight and low-power secure products.” For more information about the embedded AndesCore™ SN8 series, please refer to www.andestech.com or contact sales@andestech.com
Andes Leads The Industry by Reducing Power Consumption for New Embedded Devices New Lower-Power Processor Solutions for Wearable Computing, IOT and other Power-Critical Applications
【Santa Clara, CA, October 2, 2013】 – Andes Technology (www.andestech.com), Asia’s leading supplier of licensable processor cores, today disclosed plans for a new class of ultra-low power processor core solutions. These products will incorporate a new technology called FlashFetch™ as well as other energy reducing innovations. Collectively, these new capabilities are designed to meet the most demanding, power-sensitive requirements for applications such as Wearable Computing devices, IoT (Internet of Things) and other flash-memory based requirements. Building upon Andes’ successful line of performance-efficient IP cores, already in hundreds of millions of products, the company is breaking new ground by further reducing energy consumption and extending battery life to enable a new class of devices.
Speaking from TSMC’s Open Innovation Platform(OIP) ecosystem conference, Andes’ President, Frankwell Lin, explained: “Reducing energy consumption is a global need and we are committed to help that through innovations in performance-efficiency. These new products enable our customers to rebalance performance and power consumption, resulting in SOCs that consume less energy to accomplish their work. This helps extend battery life for the next generation of embedded devices – like the new Wearable Computing products that are starting to emerge.” Andes is demonstrating their entire product line at their booth at the OIP conference.
Andes new low power solutions have impact beyond the processor cores. The techniques used allow lower speed memories to be used, saving power without sacrificing performance and also enable the creation of off-core program buffers. Moreover, modeling application performance of is simplified with the AndesSight™ development environment. This allows customers to experiment with alternate hardware approaches to optimize power, performance and size for their specific software.
“As the new class of SoC solutions for IoT applications becomes better defined, one trend that is emerging is the need for very low power consumption and high power efficiency in the silicon,” said Rich Wawrzyniak, Sr. market Analyst at Semico Research. “Approaches and products that allow designers to realize good performance while delivering power efficiency will be well-received in the market and enjoy a large degree of success.” Wawrzyniak went on to say, “the research Semico is doing today on IoT applications shows the potential for very large unit volumes in the near future to support IoT implementations in both consumer and commercial environments. Good solutions in one area have the potential of being adopted in other areas of the market and the Andes Technology use of the FlashFetch technology can impact silicon solutions aimed at these other market segments. This design solution can have a synergistic effect on Andes’ growth into these newer market segments.”
These new low power solutions featuring FlashFetch, COPILOT, PowerBrake and other new techniques will be discussed at the upcoming Linley Tech Processor Conference on October 16th and 17th at Hyatt Regency, Santa Clara.
For more information about the AndesCore™ N7 Series, FlashFetch or any of our other low-power, high-performance IP cores and subsystems, please refer to www.andestech.com or contact us at america@andestech.com
Andes Embedded Processor Symposium 2013 Held in Korea
Co-organized by Andes and KIPEX, Andes Embedded Processor Symposium 2013 was held on Sep 12, 2013 at EL Tower, Seoul, Korea. Specially designed for embedded SoC designers and ASIC design service companies, speeches focused on Andes high performance, low power 32-bit processors and the associated SoC development platforms. Attendees were introduced to new-generation SoC solutions that meet rapidly-growing demands on better scalability, flexibility, performance, cost and power saving.
In the symposium, Andes Sales VP presented three major trends of device creation, the evolution of embedded CPUs and the MCU market analysis; Andes FAE Director introduced Andes advantages in hardware for MCU applications and Linux applications; Andes Sr. Technical Manger introduced Andes proprietary instruction set architecture AndeStar™, Andes software development environment AndeSight™ and complier optimization.
The symposium will be held periodically in the future. Through the event, Andes plans to bring the first hand technology development to the Korean industry and enhance interaction with customers there.
