Andes Announces over 1.2 GHz RISC-V Cores Series at 28nm: A25/AX25 and N25F/NX25F

Andes Technology Corporation (TWSE:6533), a founding member of the RISC-V Foundation and the leading Taiwan-based supplier of 32/64-bit embedded CPU cores with solutions serving in excess of 2.5-Billion SoCs covering a wide range of applications, today announced the availability of the latest four members of the AndeStar™ V5 high efficiency processor series: (1) the AndesCore™ A25/AX25, perfect for Linux-based applications such as UAV(Unmanned Aerial Vehicle), smart wireless communication, networking, video processing, ADAS (Advanced Driver Assistance Systems), storage, data center, and machine/deep learning; and (2) the AndesCore™ N25F/NX25F, that can be used for a wide range of floating-point intensive applications including advanced motor control, satellite navigation, high-precision sensor fusion, and advanced smart meters.

The A25/N25F are 32-bit CPU IP cores, and AX25/NX25F are 64-bit ones. All of them are capable of operating over 1.2 GHz at the worst-case corner of TSMC 28nm HPC+ process, delivering over 3.5 CoreMark/MHz, and 1.3 MWIPS/MHz for single precision floating point. Their common features include dynamic branch prediction, instruction and data caches, Local Memories for low-latency accesses, L1 memory ECC for soft error protection, and Andes Custom Extension™ (ACE) to greatly simplify instructions design for Domain-Specific Acceleration (DSA). All cores support User/Machine Mode (U/M mode) while the A25/AX25 add Supervisor Mode (S-mode) and memory management unit (MMU) to run Linux kernel and its applications. In the floating point side, the N25F/NX25F support IEEE754-compliance with either single precision or single/double precisions. Andes further extends floating-point support to half precision for applications such as machine learning, where loads/stores automatically convert 16-bit half-precision data to/from single precision data. The A25/AX25 also optionally support all the floating-point features mentioned above. All processors are offered in human-readable and tool-friendly Verilog RTL and with a GUI tool for designers to flexibly choose their final configurations.

“Andes adopted RISC-V as the subset of its fifth generation architecture, the AndeStar™ V5, and brings it to the RISC-V community,” Dr. Charlie Su, CTO and Senior VP of Andes Technology commented, “The A25/AX25 and the N25F/NX25F are versatile processors with a 5-stage pipeline and RISC-V compliant ISA (RV-IMAC[FD]). All 25-series processors include Andes-enhanced Platform-Level Interrupt Controller (PLIC) with vectored interrupt dispatch and priority-based preemption for efficiently serving various types of system events, and can be pre-integrated with 64-bit AXI or 64/32-bit AHB bus platforms. They also bring to RISC-V common cache features for embedded systems such as finer-grained cache management, write-back and write-through modes, and uncached accesses. In addition, PowerBrake, QuickNap™ and WFI (Wait for Interrupt) operation together enable various power modes to address application needs; JTAG and 2-wire interfaces are available for debug and trace support; the StackSafe™ protects the software stack from overflow and underflow; and the Andes’ patented CoDense™ enhances code density on top of RISC-V C-extensions. It also supports misaligned memory accesses directly in hardware, which is good for porting existing software from ARM and x86; without it, more than 100 cycles may be required in the exception handler. They have been selected by our customers for their exceptional performance/power, flexible configurations, highly optimized compiler and comprehensive development tools. We are also engaged with 3rd party partners to provide more development tools, IPs, and runtimes, including fast system simulators, security subsystems, SoC analytics, tracer and debugger, software stacks and more. “

The V5 AndesCores inherit the compact, modular and extensible advantages from the RISC-V technology and also enjoy its fast-growing ecosystem. In addition to full compatibility to RISC-V technology by supporting its standard instructions, AndeStar V5 architecture brings Andes-extended features already proven in high-volume V3 AndesCores to be effective and beneficial to embedded applications.

Andes is a major contributor to the RISC-V open source software, ranging from GCC and LLVM compilers, libraries, debuggers, to U-Boot and the Linux kernel and its key components. In addition, Andes also plays a key role to grow the RISC-V architecture, acting as the chair of ISA P-extension (Packed DSP) Task Group and the co-chair of Fast Interrupt Task Group. Andes is committed to taking RISC-V mainstream by helping accelerate the ecosystem growth together with partners.

 

Continue ReadingAndes Announces over 1.2 GHz RISC-V Cores Series at 28nm: A25/AX25 and N25F/NX25F

GOWIN Semiconductor Licenses Andes Technology RISC-V CPU Core For Its Arora® GW-2A FPGA Family Products

Andes Technology Provides GOWIN Standard RISC-V CPU ISA, 
Plus Enhanced Features for Performance, Reliability, Program Code Size and Power Consumption

HSINCHU, TAIWAN & GUANGZHOU, CHINA – October 01, 2018—Andes Technology Corporation, the leading Asia-based supplier of small gate count, low-power and high performance 32/64-bit embedded CPU cores, announces that GOWIN Semiconductor has licensed Andes Technology’s RISC-V CPU core for its Arora® GW-2A FPGA family of products. Besides the standard RISC-V ISA, the Andes Technology RISC-V CPU comes with additional features to improve performance, reliability, program code size and power consumption reduction.

“Adding the Andes RISC-V to our Arora Family of FPGA’s provides fast time to market for engineers wanting to implement a design using the RISC-V CPU,” said Scott Casper, Director of Sales for GOWIN’s Americas Region. “The CPU core can be implemented in a relatively small number of FPGA logic elements thus providing additional capacity for the engineer’s logic design.  Having Andes as a partner has enabled GOWIN to quickly supply customer demand for this popular CPU ISA.”

“We are thrilled that GOWIN has chosen the Andes RISC-V CPU core for their Arora® GW-2A FPGA Family products,” said Vivien Lin, Vice President of Sales Andes Technology USA Corp. “Demand for the Andes RISC-V CPU offering is growing and having GOWIN offering an FPGA version combined with the Andes RISC-V  Eclipse-based development environment provides designers a fast track to develop their offering.”

About GOWIN Semiconductor Corp.
Founded in 2014, GOWIN Semiconductor Corp., headquartered with major R&D in China, has the vision to accelerate customer innovation world-wide with their programmable solutions. GOWIN focuses on optimizing their products and removing barriers for customers using programmable logic devices. GOWIN’s commitment to technology and quality enables customers to reduce the total cost of ownership from using FPGA on their production boards. GOWIN’s offerings include a broad portfolio of programmable logic devices, design software, intellectual property (IP) cores, reference designs, and development kits. GOWIN strive to serve customers in the consumer, industrial, communication, medical, and automotive markets worldwide. For more information about GOWIN, please visit www.gowinsemi.com.

About Andes Technology Corporation
Andes Technology Corporation was founded in Hsinchu Science Park, Taiwan in 2005 to develop innovative high-performance/low-power 32/64-bit processor cores and associated development environment to serve worldwide rapidly growing embedded system applications. The company delivers the best super low power CPU cores, including the rising star RISC-V series with integrated development environment and associated software and hardware solutions for efficient SoC design. Up to the end of 2017, the cumulative amount of SoCs containing Andes’ CPU IP reaches 2.5 billion. To meet the demanding requirements of today’s electronic devices, Andes Technology delivers configurable software/hardware IP and scalable platforms to respond to customers’ needs for quality products and faster time-to-market. Andes Technology’s comprehensive CPU line includes entry-level, mid-range, high-end, extensible and security families to address the full range of embedded electronics products, especially for connected, smart and green applications. From 2017, Andes expanded its product line and provides a total solution of RISC-V, the RISC-V series as V5 families processors cores include 32/64-bit N25/NX25 for general purpose, N25F/NX25F for floating-point intensive applications and A25/AX25 for Linux-based applications. For more information about Andes Technology, please visit http://www.andestech.com/.
 

Continue ReadingGOWIN Semiconductor Licenses Andes Technology RISC-V CPU Core For Its Arora® GW-2A FPGA Family Products

Webinar: Introduction to Andes Superscalar Processors – N15(F)/D15(F)

Watch the recording and dowload the slides below.

Date: July 31, 2018 (Tue.)
Time: 16:00 – 16:40 (GMT+8)
Topic: Introduction to Andes Superscalar Processors – N15(F)/D15(F)

Abstract: Increasingly IC design companies are looking to integrate higher performance/power/area efficiency cores into their SoCs for a wide range of applications such as sensors, smart meters, biometric, communication, audio/voice processing, image processing, medical devices, industrial applications, GPS, drones, etc. Given that, Andes is very pleased to offer a series of 4 AndeStar™ V3-based superscalar processors, the AndesCore™ N15/N15F/D15/D15F, to address the demanding needs. In this 40-min webinar, the presenter will introduce these processors with the following agenda,
– Product Highlights
– Applications
– Functional Blocks
– Feature Introduction
– Performance Benchmark & Comparison
– Ecosystem Support and Service
– Concluding Remarks
– Q & A

Presenter: Vincent Chen, Director of Marketing & Service Division of Andes Technology Corporation, has more than 20 years of experience in IT industry. Prior to joining Andes Technology, he took senior product marketing or technical manager roles for the leading companies, like Intel and CEVA. He received bachelor and master’s degrees from National Chiao-Tung University, Hsinchu, Taiwan.

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Andes Technology Corporation and XtremeEDA Corporation Cooperate to Develop Joint Design Wins on Emerging RISC-V Designs

Andes to Offer Its Low-Power, High Performance CPU Cores, Including New RISC-V IP;
XtremeEDA to Provide Its Front-end IC Design Expertise to Reduce Designers’ Time to Market
 

Andes Technology Corporation, the leading CPU IP supplier of small, low-power, high performance 32/64-bit embedded CPU cores, and XtremeEDA Corporation, a leading North American provider of front-end design and verification services for the semiconductor industry, today announced they will cooperate to develop joint design wins to benefit both companies. Andes will provide Its low-power, high performance CPU cores, including the first RISC-V core from a public semiconductor company; XtremeEDA will provide experienced front-end design and verification services, thus collectively reducing designers’ time to market.

“We are excited to be joining forces with XtremeEDA to provide our customers CPU IP and design resources they may not possess internally,” said Emerson Hsiao, Senior Vice President of Sales and Technical Service at Andes Technology Corporation USA. “In today’s embedded systems-on-chip (SoC) market, an increasingly important variable in how chips are designed and produced is time to market. A new start-up may have a great architectural specification but may lack the team, design tools, and IP needed to convert the design idea into a chip. In addition, many cannot afford the high cost for design verification.  Together XtremeEDA and Andes can offer its customers access to a design and verification team and a library of IP to support the Andes core that will provide reduced time to market for their unique design.”

“Andes represents a great supplement to our own sales and marketing effort,” said Chris Raeuber, XtremeEDA’s Director of Engineering, US. “As a major CPU core supplier in Asia, Andes has great market insight into the new designs going on in that region and they are bringing that knowledge to the U.S. They are identifying start-ups with unique new SoCs targeting emerging markets that need front-end and verification engineering resources, such as what we offer.  Together, we provide our mutual customers a means of rapidly getting their designs into silicon.”

Complementary Strengths
One service Andes provides its customers is an FPGA based version of its processor IP on a reference platform including the new RISC-V IP core. Prospects can evaluate the Andes core using the reference board. In many instances, once a prospect becomes a customer, he may decide to use a design services supplier to take the FPGA implementation and convert it into an SoC chip design. Having XtremeEDA, who is familiar with the Andes reference platform, to convert the FPGA implementation to an SoC chip design greatly shortens the customer’s time to market.

About XtremeEDA Corp.
Founded in 2002, XtremeEDA is a North American based provider of front-end design and verification services for the semiconductor industry.  Our team is unparalleled – with employees averaging 20+ years of semiconductor industry experience and expertise that spans most major sectors. Our business approach emphasizes enduring and transformational relationships to employ creative solutions that enable extraordinary results for all stakeholders. For more information, please visit https://www.xtreme-eda.com

Continue ReadingAndes Technology Corporation and XtremeEDA Corporation Cooperate to Develop Joint Design Wins on Emerging RISC-V Designs