HunterSun Corporation Licenses AndesCore™ N1068A-S for Its HS6601 Single-Chip Bluetooth SoC Targeting Wireless Audio Applications

Andes’ N1068A-S Provides Design Flexibility and Balances Performance and Power Consumption for Wireless Audio Applications
 

HSINCHU, TAIWAN – June 20th , 2018 – Andes Technology Corporation, the leading Asia-based supplier of small, low-power, high performance 32/64-bit embedded CPU cores, today announced that HunterSun Corporation has licensed its mid-range AndesCore™ N1068A-S for the HunterSun HS6601 single-chip Bluetooth SoC that receives wireless audio, drives speakers and digitizes microphone input.  Andes’ N1068A-S provides design flexibility and required computing power for processing Bluetooth protocol with Enhanced Data Rate (EDR) functionality and combining audio processing and applications.

“Andes Technology’s N1068A-S provided our engineering team, a highly integrated, lower cost solution for our HS6601 single-chip Bluetooth,” said Xiaobin Ye, Senior Vice President of HunterSun Corp. “The demand for Bluetooth SoCs in audio applications is extremely strong in China. With the Andes CPU, we were able to integrate Bluetooth stack and required profiles with our audio framework expertise while providing FM radio and I/O functionality for USB and SD memory demanded in most of the audio applications.  Incorporating all this functionality on chip enabled us to gain an advantage in this highly competitive product segment.”

“We are extremely pleased that HunterSun chose our N10 CPU IP for their HS6601 Bluetooth Chip,” said Charlie Hong-Men Su, Andes CTO and Senior Sales Vice President. “The AndesCore™ N10 processor is ideal for HunterSun’s Bluetooth audio application with a balance of performance and power consumption. The N10’s 5-stage pipeline and the rich AndeStar™ Instruction-Set Architecture provides plenty of performance headroom to accommodate the evolution of the Bluetooth dual mode specification and to support a wide range of audio applications by the HunterSun SoC.  The N1068A-S also comes with instruction and data cache and local memory options. These enable the system to provide both power and design efficiency to perform a combination of wireless communication and multimedia processing.”

About HunterSun Corporation
HunterSun Corporation is a high-tech enterprise located in Zhongguancun Science and Technology Park, co-founded by domestic and international experts in integrated circuits and electronics. The company is focused on the development of RF integrated circuit chips, analog integrated circuit chips, and System-on-Chip. The product portfolio currently includes wireless communications chips, power management chips, RF front-end modules, etc. HunterSun is also committed to develop core technology and solutions of the “Internet of things”. The products are applied in the fields of smart phone, feature phone, tablet personal computer, wireless mouse, keyboard and smarthome, etc.

HunterSun headquarter is located in Beijing. Beijing HunterSun Company is mainly responsible for the operations. HunterSun has its research and development centers in Beijing and Shanghai. Additionally, HunterSun has established its marketing and sales and technology support offices in Hong Kong, Shanghai and Shenzhen. HunterSun currently has 150 employees, and for RD group, 80% of its employees have a master degree or above; 10% of them are holders of PhD

Continue ReadingHunterSun Corporation Licenses AndesCore™ N1068A-S for Its HS6601 Single-Chip Bluetooth SoC Targeting Wireless Audio Applications

Imperas and Andes Extend Partnership, Delivering Models and Virtual Platforms for Andes RISC-V Cores with New AndeStar V5m Extensions

AndeStar V5m Extensions for AndesCore N25 and NX25 Processors Now Supported by Imperas Virtual Platform Software Solutions and Models

Oxford, United Kingdom, May 1, 2018 — Imperas Software Ltd., the leader in virtual platforms and high-performance software simulation, and Andes Technology Corporation, today announced Open Virtual Platforms™ (OVP™) models and virtual platform support for powerful new extensions in the AndesCore™ N25 and NX25 IP processors, which are AndeStar™ V5 32-bit and 64-bit architectures based on the RISC-V technologies.

Building on the Imperas and Andes partnership to support Andes’ RISC-V cores announced in November 2017, the new Imperas reference models support the Andes AndeStar™ V5m extensions.

Imperas is the leading provider of RISC-V processor models and virtual prototype solutions, including both of the Andes N25 32-bit and NX25 64-bit cores. The new Andes models, with extensions, are available now from Imperas and the Open Virtual Platforms (OVP) website.

Andes is the leading Asia-based supplier of small, low-power, high performance 32/64-bit embedded CPU cores for a full range of embedded electronics products, including low-cost embedded applications, data centers and artificial intelligence (AI), connected, smart and green applications, machine-learning accelerators, communications, security, IoT, and consumer applications.

Charlie Hong-Men Su, Ph.D., Andes Technology CTO and Senior VP, commented, “The Imperas virtual platform solutions for software development, debug and test, along with their open-source models, will help accelerate embedded software development for SoCs capitalizing on our new extensions to the V5 AndesCore N25 and NX25 processors.”

“The momentum for RISC-V is accelerating, and Andes is the first established CPU intellectual property (IP) vendor to offer a RISC-V processor for licensing. We are pleased to support their new AndeStar V5m extensions in the OVP models of their 32-bit/64-bit CPU cores, based on RISC-V,” said Simon Davidmann, president and CEO of Imperas.

Imperas delivers a comprehensive environment for embedded software development, debug and verification for Andes N25 and NX25 processors, including open-source Fast Processor Models; extendable virtual platforms including cores and peripherals; high-performance simulation; analytical tools for hardware-dependent multicore software development, debug and test including OS-aware tools. The Extendable Platform Kits (EPKs) for Andes cores run FreeRTOS, and also support heterogeneous designs with mixtures of Andes processors and other vendors’ cores including application processors.

Imperas will provide highlights of these models and virtual platforms for RISC-V designs, based on Andes cores, with the new AndeStar V5m extensions, at the upcoming 8th RISC-V Workshop, Barcelona and the Andes Forum on May 3, 2018 in Taiwan.

These models of the extended Andes cores expand Imperas and OVP processor support to over 200 models across a wide variety of vendors. For the latest list of Imperas models, please see www.OVPworld.org. 

About Andes Technology Corporation
Andes Technology, the first CPU IP supplier in Asia, has been devoting to the development of innovative high-performance/low-power 32/64-bit processors and associated SoC platforms since its foundation in 2005. Its powerful CPU lineup covering entry-level, mid-range, high-end, extensible and security families has achieved design wins in numerous embedded applications across the world, making a cumulative record of over 2.5 billion SoC shipment containing Andes IP up to 2017. While delivering advanced features based on proprietary ISAs, Andes is also the first mainstream CPU vendor adopting the open RISC-V.
For more information please visit: http://www.andestech.com/

About Imperas
For more information about Imperas, please see www.imperas.com. Follow Imperas on LinkedIn, twitter @ImperasSoftware and YouTube.

All trademarks or registered trademarks are the property of Imperas Software Limited or their respective holders.

Continue ReadingImperas and Andes Extend Partnership, Delivering Models and Virtual Platforms for Andes RISC-V Cores with New AndeStar V5m Extensions

UltraSoC selected by Andes for RISC-V development with trace and debug

UltraSoC today announced that Andes Technology, the leading and established CPU IP supplier in Asia, has adopted UltraSoC’s advanced embedded analytics technology for use in its AndesCore range of RISC-V processors. Andes will leverage UltraSoC’s unique intellectual property (IP) offering, including the industry’s only commercial RISC-V processor trace solution, to accelerate development and enhance debugging of embedded products for sophisticated applications including Artificial Intelligence (AI), computer vision, network controllers, and storage.

The two companies will collaborate to demonstrate a complete RISC-V development, debug, and trace flow at the upcoming RISC-V Workshop (May 7 – 10, Universitat Poletècnica de Catalunya, Spain).

UltraSoC is the only company offering a commercial RISC-V development environment, with SoC analytics, processor trace and other options available to meet the needs of end customers. A pioneer in the industry, UltraSoC developed processor trace for RISC-V in 2017, and shortly afterwards offered its trace specification for use by the RISC-V Foundation as part of its standardization effort. The company remains fully committed to supporting the RISC-V Foundation standard run-control/debug and the proposed processor trace format, in line with its wider strategy of providing integrated debug and development solutions for any processor architecture.

Andes’ cores are based on the high-performance AndeStar V5 32-bit and 64-bit architectures. The partnership with UltraSoC allows customers for Andes V5 N25 and NX25 processors to have advanced embedded analytics capabilities integrated as an option. Customers using Andes’ high-performance 32 and 64-bit processor cores gain access to UltraSoC’s SoC analytics and debug IP in addition to RISC-V processor trace, which together give designers full visibility not only of the performance of the core but into the operation of the entire system.

Andes has adopted RISC-V for its fifth generation processor architecture, the AndeStar V5, and launched two high-end processor cores in its AndesCore family of configurable processor IP: the 32-bit N25 and the 64-bit NX25. Both are RISC-V based and deliver in excess of 3.4 CoreMark/MHz, with gate counts as small as 30K (N25) and 50K (NX25), and a maximum clock rate of 1.1 GHz when using TSMC’s 28nm HPC process. The N25 and NX25 are both ideal for high-speed control tasks, and customers choosing either core will benefit from access to UltraSoC’s embedded intelligence.

Charlie Su, CTO and Senior VP of Andes, commented: “The N25 and NX25 AndesCore processors are selected by our customers for their exceptional performance/power, flexible configurations, and comprehensive development tools. Choosing UltraSoC as our preferred partner for embedded analytics, trace and validation gives our customers an advanced development environment with insight into SoC operations and processor execution without disturbing target behaviour. UltraSoC has shown itself to be committed to the development of the RISC-V ecosystem and hence it is clearly the best partner for our V5 RISC-V architecture. We are delighted to already be engaged with multiple mutual customers using Andes processor N25/NX25 with UltraSoC’s IP and trace solution to address their demanding applications.”

Rupert Baines, CEO of UltraSoC commented: “We are delighted to be working with Andes on its innovative processor cores for RISC-V, and collaborating with mutual customers on implementations which utilize the power of its leading V5 AndeStar architecture and enable designers full access to the system with the support of UltraSoC’s SoC analytics and debug IP, and processor trace.”

RISC-V is an open source instruction set architecture, initially developed by UC Berkeley now being rapidly more widely adopted. UltraSoC and Andes are active members of the RISC-V Foundation, and play active roles in its development. Both companies also participate in all RISC-V Workshops, and will be involved in the upcoming 8th RISC-V workshop in Barcelona.

UltraSoC is committed to offering the best tools for giving designers of complex systems invaluable insight into the performance of both hardware and software, throughout any electronic system – and importantly, during its operation, not only during its design. The benefits this delivers have significant impact on safety, security, performance and power consumption. Designers are able to monitor, to understand how hardware and software are working together, and to fine-tune a system, even when it is incorporated into an overall system design. Using UltraSoC embedded analytics can slash development costs by 25% as well as the incalculable savings and competitive advantages of avoiding redesigns, and improvements in time to market.

About Andes Technology

Andes Technology, the first CPU IP supplier in Asia, has been devoting to the development of innovative high-performance/low-power 32/64-bit processors and associated SoC platforms since its foundation in 2005. Its powerful CPU lineup covering entry-level, mid-range, high-end, extensible and security families has achieved design wins in numerous embedded applications across the world, making a cumulative record of over 2.5 billion SoC shipment containing Andes IP up to 2017. While delivering advanced features based on proprietary ISAs, Andes is also the first mainstream CPU vendor adopting the open RISC-V.

For more information please visit: http://www.andestech.com/

Continue ReadingUltraSoC selected by Andes for RISC-V development with trace and debug

SiFive Inc. and Andes Technology Corporation Join Forces to Promote RISC-V

Two Leading RISC-V Suppliers Agree to Cooperate to Further Promote RISC-V Adoption while Continuing to Aggressively Expand the RISC-V Ecosystem
 
Shanghai and San Mateo, Calif.—July 13, 2018— Andes Technology Corporation, the prominent CPU IP provider, and SiFive Inc., the leading provider of ASIC design service and RISC-V CPU Core IP, have announced they are joining forces to jointly promote RISC-V. The two companies will each contribute their unique expertise in CPU development and support to expand the ecosystem for the RISC-V instruction set architecture (ISA) to enable a new era of processor innovation through open standard collaboration. 


“RISC-V is providing a newfound freedom in silicon design, fostering stronger collaboration across the semiconductor industry. We’re excited to see SiFive and Andes partnering to expand the RISC-V ecosystem, making it easier for other industry players to quickly bring to market innovative designs based on the open RISC-V ISA,” said Rick O’Connor, Executive Director of the non-profit RISC-V Foundation.
 
As a founding member of the RISC-V Foundation, Andes Technology is dedicated to bringing its expertise in low-power and high performance 32/64 bit processor cores to the development of the RISC-V ISA. For example, at the recent RISC-V Workshop in Barcelona, Andes proposed an extension to the RISC-V ISA based on the DSP ISA used in Andes’ successful D10 and D15 processors. In addition, Andes debuted four new RISC-V processor IPs with compliant floating-point and Linux support: the 64-bit NX25F and AX25, and 32-bit N25F and A25. Andes’ innovative ACE (Andes Custom Extension™) solution allows Andes’ customers to construct unique system architecture and hardware/software partitioning by defining domain-specific acceleration instructions to provide the best optimization for their SoC designs. Offering technologies in processor, system architecture, operating system, software toolchains development, and SoC design platforms IP, Andes enables its customers to shorten time-to-market while developing high-quality silicon in the shortest design time.
 
SiFive’s cloud-based SaaS approach allows its customers to produce ASIC and IP solutions that meets their needs quickly and affordably. SiFive’s mission is to democratize access to custom silicon through its IPs and platforms. Since becoming available, the HiFive1 and HiFive Unleashed software development boards have been deployed in more than 50 countries. Additionally, the company has engaged with multiple customers across its IP and SoC products shipped the industry’s first RISC-V SoC in 2016 and the industry’s first RISC-V Core IP with support for Linux in October 2017.
 
Led by a team of industry veterans and founded by the inventors of RISC-V, SiFive has recently raised $50.6M in Series C funding to fund innovation and provide leadership in bringing highly disruptive RISC-V technologies to the marketplace.
 
RISC–V Enables Innovation
RISC-V is an open ISA enabling a new era of processor innovation through open standard collaboration. Born in academia and research, the RISC-V ISA delivers a new level of extensible software and hardware freedom on architecture, paving the way for the next 50 years of computing design and innovation. As the focus of a new upsurge in technology, RISC-V has flourished around the world. RISC-V is the new open ISA, which is compact, modular and extensible. It enables the rapid development of a design ecosystem. A large and growing number of leading technology companies have joined the RISC-V Foundation. SiFive and Andes have chosen Shanghai as the ideal location to relay efforts in promoting RISC-V to the world.
 
RISC-V is an open, extensible ISA, and its applications include the emerging areas such as AI, IoT, and ADAS. Its expansive ecosystem is even more valuable. The RISC-V ISA is expected to have a bright future of computing design in China.
 
About SiFive
SiFive is the leading provider of market-ready processor core IP based on the RISC-V instruction set architecture. Founded by the inventors of RISC-V, SiFive helps SoC designers reduce time-to-market and realize cost savings with customized, open-architecture processor cores, and democratizes access to optimized silicon by enabling system designers to build customized RISC-V based semiconductors. SiFive is located in Silicon Valley and has venture backing from Sutter Hill Ventures, Spark Capital, Osage University Partners and Chengwei Capital, along with strategic partners Western Digital, Intel, SK Telecom, and Huami. For more information, visit www.sifive.com.
 
About Andes
Andes Technology Corporation was founded in Hsinchu Science Park, Taiwan in 2005 to develop innovative high-performance/low-power 32/64-bit processor cores and associated development environment to serve worldwide rapidly growing embedded system applications. 
The company delivers the best super low power CPU cores, including the rising star RISC-V series with integrated development environment and associated software and hardware solutions for efficient SoC design. Up to the end of 2017, the cumulative amount of SoCs containing Andes’ CPU IP reaches 2.5 billion.
To meet the demanding requirements of today’s electronic devices, Andes Technology delivers configurable software/hardware IP and scalable platforms to respond to customers’ needs for quality products and faster time-to-market. Andes Technology’s comprehensive CPU includes entry-level, mid-range, high-end, extensible and security families to address the full range of embedded electronics products, especially for connected, smart and green applications. From 2017, Andes expands its product line and provides a total solution of RISC-V, the RISC-V series as V5 families processors cores include N25/NX25 and upcoming N25F/NX25F and A25/AX25.  
For more information about Andes Technology, please visit http://www.andestech.com/.
 
PRESS RELEASE
 
Media Contacts:
Leslie Clavin 
SHIFT Communications for SiFive
(415) 591-8440
sifive@shiftcomm.com
 
Media Contact:
Jonah McLeod
Andes Technology Corporation
(510) 449-8634
jonahm@andestech.com
 

Continue ReadingSiFive Inc. and Andes Technology Corporation Join Forces to Promote RISC-V