Read more about the article Rain AI Unveils Andes Technology as Its RISC-V Partner

Rain AI Unveils Andes Technology as Its RISC-V Partner

Rain AI Licenses Andes AX45MPV and Taps Andes Custom Computing BU to Accelerate Its Launch of Groundbreaking Compute-In-Memory (CIM) Generative AI Solutions

San Francisco, CA, June 03, 2024 – Andes Technology, a leading supplier of high-efficiency, low-power 32/64-bit RISC-V processor cores and Founding Premier member of RISC-V International announces that Rain AI, a pioneer in compute-in-memory (CIM) technology, licensed Andes’ AX45MPV RISC-V vector processor. Rain AI designs novel accelerator solutions, and the two companies are collaborating to accelerate Rain AI’s product roadmap.

As the world economy embraces generative AI to deliver unprecedented benefits to consumers and business alike, energy consumption stands as a significant hurdle regardless of the deployment points, be it the cloud, edge, and especially the smallest sensors. CIM represents the most promising solution to lower the energy footprint by as much as 50X. By performing computations directly in the memory bit-cells, CIM can dramatically reduce the energy required for matrix operations commonly found in machine learning.

However, CIM by itself cannot completely address the vast and growing number of machine learning operators. A RISC-V CPU is ideal for efficient programming and future-proofing of an CIM-based NPU.  The RISC-V architecture allows users to add custom instructions to encapsulate the CIM computing blocks, easing software development efforts.  Andes automates this instruction customization process with its automated COPILOT compiler.

Mr. Frankwell Lin, Chairman and CEO of Andes, says, “Andes is honored and excited to have Rain AI as its licensee and partner.  As the first RISC-V vector processor provider, we see CIM as an inevitable necessity to enable generative AI applications and therefore have focused on CIM customers.  To our knowledge, Rain AI has designed one of the most energy efficient matrix multiplication units using digital CIM technology, so we look forward to Rain AI unveiling its breakthrough solutions.”

Mr. William Passo, CEO of Rain AI, echoed this sentiment, stating, “It is rare to see a vendor who shares the same market and technology vision as us, has best-in-class RISC-V solutions for our technology needs, and can commit resources to help us accelerate our roadmap to significantly reduce the energy required for AI.  Running the most advanced models in any form factor is the future of AI, and we are now one step closer with Andes.”

Indeed, Rain AI further taps into Andes’ Custom Computing Business Unit (CCBU) to help accelerate the integration of Andes AX45MPV and the ACE/COPILOT instruction customization with on-site and remote consulting services. Andes’ CCBU is a small team of experts tasked to perform complex customizations and integrations for a few promising cutting-edge licensees. 

Both companies can share that AX45MPV and Andes’ unique RISC-V instruction customization solution, ACE/COPILOT both play pivotal roles to complement Rain AI’s groundbreaking CIM hardware, compiler, and runtime software to deliver scalable ML solutions for a variety of deployment points. Rain AI will unveil its accelerator solution in early 2025.

About Andes Technology
Nineteen years in business and a Founding Premier member of RISC-V International, Andes is a publicly-listed company (TWSE: 6533; SIN: US03420C2089; ISIN: US03420C1099) and a leading supplier of high-performance/low-power 32/64-bit embedded processor IP solutions, and the driving force in taking RISC-V mainstream. Its V5 RISC-V CPU families range from tiny 32-bit cores to advanced 64-bit Out-of-Order processors with DSP, FPU, Vector, Linux, superscalar, functional safety and/or multi/many-core capabilities. By the end of 2023, the cumulative volume of Andes-Embedded™ SoCs has surpassed 14 billion. For more information, please visit https://www.andestech.com. Follow Andes on LinkedIn, Twitter, Bilibili and YouTube! ! 

About Rain AI
Rain AI’s mission is to enable advanced and abundant AI everywhere by building the world’s most efficient AI hardware. It creates flexible solutions for generative AI inference and training utilizing novel compute-in-memory CIM technology, RISC-V processing cores, advanced packaging techniques, and optimized ML algorithms. By co-designing hardware with leading AI models, Rain AI sets new standards in AI efficiency and performance. Rain AI investors include Sam Altman, Dan Gross, and Y Combinator. For further information, visit http://www.rain.ai.

Continue ReadingRain AI Unveils Andes Technology as Its RISC-V Partner
Read more about the article Andes Technology and Arteris Partner To Accelerate RISC-V SoC Adoption

Andes Technology and Arteris Partner To Accelerate RISC-V SoC Adoption

Highlights:
– Andes Technology and Arteris partnership aims to support the growing adoption of RISC-V SoCs by mutual customers.
– Focus is on high-performance/low-power RISC-V-based designs across a wide range of markets, including consumer electronics, communications, industrial applications and AI.
– The collaboration showcases integrated and optimized solutions with leading Andes RISC-V processor IPs and Arteris interconnect IP in silicon.

CAMPBELL, Calif. – May 21, 2024 – Arteris, Inc. (Nasdaq: AIP), a leading provider of system IP that accelerates system-on-chip (SoC) creation and Andes Technology (TWSE: 6533), a founding and premier member of RISC-V International and a leading supplier of high-performance/low-power RISC-V processor IP, today announced their partnership to advance innovation for RISC-V based SoC designs for AI, 5G, networking, mobile, storage, AIoT and space applications.

The Andes QiLai RISC-V platform is a development board with a QiLai SoC featuring the Andes’ RISC-V processor IPs along with Arteris FlexNoC interconnect IP used for on-chip connectivity. The QiLai SoC integrates the Andes 64-bit AX45MP multiprocessor (four cores in a cluster) running at 2.2 GHz and the NX27V vector processor running at 1.5 GHz, using Arteris network-on-chip (NoC) interconnect IP with subsystems for PCIe, DDR, SRAM and General Purpose IO using the AMBA AXI protocol. The supporting software includes the OpenSUSE Linux distribution, AndeSight™ toolchains, AndeSoft™ software stacks and AndesAIRE™ NN SDK to convert AI/ML models to executables.

“Even though AndesCore™ AX45MP and NX27V processors are widely used, we are still pleased to see the QiLai SoC achieve first time right on new projects,” said Dr. Charlie Su, Andes Technology’s president and CTO. “Arteris NoC IP was the obvious choice for flexible, high-performance, top-level connectivity across the QiLai SoC. The QiLai platform enhances the rapid development and assessment of RISC-V software, accelerating the expansion of the RISC-V ecosystem.”

“We are excited to partner with Andes Technology and support the QiLai platform interoperability to further accelerate RISC-V technology mainstream adoption,” said Michal Siwinski, chief marketing officer at Arteris. “Our collaboration supports our mission to be the catalyst for SoC innovation so our mutual customers can focus on efficiently creating tomorrow’s breakthroughs.”

Arteris’ FlexNoC non-coherent NoC IP and Ncore cache-coherent NoC IP enable scalable, low latency and power-efficient on-chip communication to achieve superior performance in complex SoC designs. The technology facilitates the integration of high-performance, low-power CPU IPs, enhancing system functionality and interoperability, especially within the growing RISC-V ecosystem. This configurable and adaptable interconnect solution seamlessly interfaces with various components to mitigate risks and expedite time to market. By connecting well-tested CPU IP blocks, system designers can leverage Arteris NoC IPs to enhance the reliability and quality of next-generation SoCs.

Customers can request a devkit featuring the Andes QiLai RISC-V platform at sales@andestech.com. For more information on the partnership and respective products, please contact info@arteris.com and info@andestech.com.


About Arteris
Arteris is a leading provider of system IP for accelerating system-on-chip (SoC) development across today’s electronic systems. Arteris network-on-chip (NoC) interconnect IP and SoC integration automation technology enable higher product performance with lower power consumption and faster time to market, delivering better SoC economics so its customers can focus on dreaming up what comes next. Learn more at arteris.com

About Andes Technology
Nineteen years in business and a founding premier member of RISC-V International, Andes is a publicly-listed company (TWSE: 6533; SIN: US03420C2089; ISIN: US03420C1099) and a leading supplier of high-performance/low-power 32/64-bit embedded processor IP solutions, and the driving force in taking RISC-V mainstream. Its V5 RISC-V CPU families range from tiny 32-bit cores to advanced 64-bit Out-of-Order processors with DSP, FPU, Vector, Linux, superscalar, functional safety and/or multi/many-core capabilities. By the end of 2023, the cumulative volume of Andes-Embedded™ SoCs has surpassed 14 billion. For more information, please visit https://www.andestech.com. Follow Andes on LinkedIn, Twitter, Bilibili and YouTube!

© 2004-2024 Arteris, Inc. All rights reserved worldwide. Arteris, Arteris IP, the Arteris IP logo, and the other Arteris marks found at https://www.arteris.com/trademarks are trademarks or registered trademarks of Arteris, Inc. or its subsidiaries. All other trademarks are the property of their respective owners.

Continue ReadingAndes Technology and Arteris Partner To Accelerate RISC-V SoC Adoption
Read more about the article Andes, HiRain, and HPMicro Join Hands to Build RISC-V AUTOSAR Software Ecosystem

Andes, HiRain, and HPMicro Join Hands to Build RISC-V AUTOSAR Software Ecosystem

May 14, 2024 —Andes, HiRain, and HPMicro jointly announced that the three parties will cooperate to combine the AndesCoreTM RISC-V processor series, the HPMicro HPM6200 full line of products, and the HiRain Vehicle OS software platform solutions to jointly build the RISC-V ecosystem in the field of automotive electronics. In this cooperation, HiRain’s AUTOSAR product INTEWORK-EAS will be adapted to HPMicro’s full line of HPM6200 products, supporting MCAL software adaptation and engineering integration for  HPMicro’s AUTOSAR solutions. HiRain is currently one of the few major AUTOSAR software suppliers with experiences in supporting multiple RISC-V automotive-grade chips. HiRain has been an active player in enabling the RISC-V AUTOSAR ecosystem.  The HPM6200 product line has 12 product models, with built-in AndesCoreTM D45 single-core or dual-core RISC-V processor. This series of products has high performance and real-time features, and its application fields include new energy, energy storage, industrial automation, electric vehicles, etc. Through this cooperation, the HPMicro’s chip products will target different application scenarios of automotive electronics with more complete functions and services, enhancing the compatibility of RISC-V technology in the field of automotive electronics. In the future, HiRain and HPMicro will continue to cooperate and continue to provide AUTOSAR software platform solutions for new products.

INTEWORK-EAS is a software product independently developed by HiRain that complies with the AUTOSAR standards. It has a complete AUTOSAR tool chain and is compatible with a variety of mainstream data formats in the industry, such as DBC, LDF, PDX, ODX, ARXML, etc. It supports seamless integration with third-party MCAL toolchains. The solution covers all aspects of standard embedded software, AUTOSAR tool chain, integration services and training, aiming to provide OEMs and suppliers with a stable, reliable, convenient, and easy-to-use AUTOSAR platform. HiRain attaches great importance to the construction of integrated software and hardware solutions. The INTEWORK-EAS series products have been extensively mass-produced and verified on internationally renowned SoC platforms, and HiRain continues to deepen its cooperation with chip companies to jointly provide more integrated software and hardware solutions to the automotive market. For HiRain, this cooperation with HPMicro adds a new important company to its chip partner list and secures its leadership position in the AUTOSAR ecosystem. 

HPMicro HPM6200 has adopted the D45 core, which has an 8-stage dual-issue superscalar design, with a main frequency of 600 MHz and performance exceeding 3390 CoreMark and 1710 DMIPS, while supporting IEEE754-compliant single/double-precision floating-point unit (FPU) and RISC-V P (draft) instructions (DSP/SIMD). The D45 core also has a memory subsystem that can support configurable instruction and data caches and local memories which can further improve software performance for the HPM6200 series SoCs. In terms of the application market, the D45 core is very suitable for embedded applications that have special requirements for fast response time and high arithmetic accuracy.

In addition to the high computing power RISC-V CPU, the HPM6200 product also integrates a series of high-performance peripherals and external storage. Further, the HPM6200 series also provides an enhanced PWM control system and a programmable logic array PLA for complex signal generation. Integrating AES-128/256, SHA-1/256 acceleration engines and hardware key managers, the HPM6200 can support hardware and software signature authentication, secure boot, and encrypted execution to prevent illegal code replacement, tampering or copying, further improving safety. HPMicro has completed the ISO9001 quality management certification and ISO 26262 functional safety management system ASIL D certification. The entire line of HPM6200 products has passed the AEC-Q100 G1 certification, with an operating temperature range of -40° to 125°C. After the HiRain INTEWORK-EAS is adapted to the HPM6200, this packaged solution will be fully promoted in the China and rest of the world automotive markets.

Jimmy Zhang, head of HiRain’s embedded software sector, said: “We are very pleased to cooperate with Andes and HPMicro. The three parties jointly create a software and hardware integration solution based on RISC-V to target the growing automotive market. In this era of rapid iteration of chips, it is important to take full advantages of the AUTOSAR middleware.  We have strong capabilities in supporting new hardware platforms and this cooperation will once again prove this. In the future, we hope to work with more partners to provide integrated solutions and promote them to the automotive industry.”

Jintao Zeng, CEO of HPMicro, said: “The D45 processor can provide high performance and low-latency for HPMicro’s MCU series products that require ultra-high-speed real-time computing. The CPU performance is excellent and in some test environments it can surpass other competing products.  Andes technical support helped us quickly and successfully complete the tape-out of the HPM6000 series. The two teams have a close and efficient cooperation.” “For HPMicro, this AUTOSAR cooperation with HiRain means that the HPMicro products have been widely recognized by the industry, and can drive adoption for high-performance microcontroller products with Andes RISC-V cores into the field of new energy electric vehicles.”

Dr. Charlie Su, President and CTO of Andes Technology, said: “The D45 core and the HPMicro HPM6200 SoC provide developers with a versatile hardware platform, allowing customers to design software with higher performance and more features.  The cooperation with HiRain and HPMicro has set a good example for the industry to take a RISC-V MCU into the wider automotive applications. We look forward to participating in more similar cooperations in the future to jointly promote great products to the automotive electronics industry.”

 

About HiRain Technology
HiRain was founded in 2003 and focuses on providing electronic products, R&D services and high-level intelligent driving overall solutions to customers in the fields of automobiles, unmanned transportation and other fields. Headquartered in Beijing, it has R&D centers and modern factories in Tianjin, Nantong and Malaysia, forming a complete R&D, production, marketing and service system. In line with the concept of “value innovation and customer service”, the company adheres to the strategies of “professional focus”, “technology leadership” and “platform development”. We are committed to becoming a world-class comprehensive electronic system technology service provider, a full-stack solution provider for intelligent connected vehicles, and a leader in high-level intelligent driving MaaS solutions. HiRain is currently one of the few suppliers that can implement full-stack solutions covering intelligent driving electronic products, R&D services and solutions. In the future, HiRain will keep up with the development trend of the automotive industry, adhere to independent innovation, strive to provide high-quality products and services to domestic and foreign customers, and contribute to the development of the automotive industry. For more information about HiRain, please visit https://www.hirain.com/.

 

About HPMicro Semiconductor
HPMicro is a semiconductor company dedicated to high-performance embedded solutions. Its products cover microcontrollers, microprocessors, and peripheral chips, as well as supporting development tools and ecosystems. The company was established in June 2020, with its headquarters located in Zhangjiang High-Tech Park, Shanghai, and branches in Tianjin, Shenzhen, Suzhou and Hangzhou. The core team comes from the management team of world-renowned semiconductor companies, with more than 15 years of rich R&D and management experience in more than 20 SoCs. HPMicro focuses on product quality, and all products pass strict reliability testing. The high-performance general-purpose MCU product series currently in mass production include HPM6700/6400, HPM6300, HPM6200, HPM5300 and HPM6800. Their performance leads similar international products and has passed AEC-Q100 certification. The company has completed ISO9001 quality management certification and ISO 26262/IEC61508 functional safety management system dual certification, and fully serves the Chinese industrial, automotive and new energy markets. HPMicro will work with world-renowned wafer fabs, packaging and testing plants and other strategic partners to jointly promote technological innovation in the semiconductor fields such as the Internet, industrial automation, and automotive electronics. For more information about HPMicro, please visit www.hpmicro.com.

About Andes Technology
Andes Technology Co., Ltd. was established in Hsinchu Science Park in 2005 and listed on the Taiwan Stock Exchange in 2017 (TWSE: 6533 SIN: US03420C2089; ISIN: US03420C1099). Andes is the founding chief member of the RISC-V International Association and the first mainstream CPU vendor to launch commercial RISC-V vector processors. To meet the strict requirements of today’s electronic equipment, Andes provides highly configurable 32/64-bit high-performance CPU cores, including DSP, FPU, Vector, Superscalar, and Out-of-Order execution, multi-core and functional safety series, which can be applied to various SoCs and application scenarios. Andes also provides a full-featured integrated development environment and comprehensive software/hardware solutions to help customers innovate their SoC designs in a short time. As of the end of 2023, cumulative shipments of Andes-Embedded™ SoC have exceeded 14 billion units. For more information, please visit https://www.andestech.com. Please follow the latest news of Andes Technology through LinkedIn, Twitter, Bilibili and YouTube now.

 

Continue ReadingAndes, HiRain, and HPMicro Join Hands to Build RISC-V AUTOSAR Software Ecosystem
Read more about the article Andes and MachineWare Collaborate on Early RISC-V Software Development for AndesCore™ AX45MPV

Andes and MachineWare Collaborate on Early RISC-V Software Development for AndesCore™ AX45MPV

Aachen, Germany and Hsinchu, Taiwan – February 27, 2024 – MachineWare GmbH and Andes Technology (TWSE:6533), a leading supplier of high-efficiency, low-power 32/64-bit RISC-V processor cores and Founding Premier member of RISC-V International announce an exciting new chapter in their collaboration, marked by a strategic partnership. This synergistic alliance is geared towards the highly innovative AndesCore™ AX45MPV, a cutting-edge multi-core RISC-V vector processor tailored for AI workload acceleration and the application level. In this joint effort, MachineWare lends its support by seamlessly integrating the AX45MPV into their SIM-V high-performance simulation solution. This integration proves invaluable for software developers, enabling them to efficiently handle intricate AI and Linux stack related workloads. The result is a platform that streamlines development, testing, and software verification well in advance of physical prototypes emerging from the fabrication process. This partnership underscores the mutual commitment of MachineWare and Andes Technology to advancing processor technology.

Introducing SIM-V, an offering from MachineWare that holds immense value for developers in the RISC-V landscape. With SIM-V, developers gain the power to thoroughly test and verify their RISC-V-based systems and software applications long before first prototypes are back from the fab. At its core, SIM-V provides a fast Instruction Set Simulator (ISS) that supports all RISC-V standard extensions. One of SIM-V‘s notable strengths is its user-friendly customizability. Through a straightforward extension SDK, developers can swiftly integrate custom instructions, registers, and other elements into the simulator to get instant feedback on their design choices. What makes SIM-V truly special is its SystemC TLM-2.0 integration. This unique combination empowers users to seamlessly introduce their IP models into full system simulation environments, enhancing the versatility of the platform.

The AndesCore™ AX45MPV is a 64-bit 8-stage dual-issue multicore RISC-V vector processor. It incorporates RISC-V GCBP* (*P is a draft version) extensions, and supports SMP Linux with MMU (Memory Management Unit) and up to 48-bit virtual addresses. In addition, it can be configured to up to eight cores with a cache coherence manager and up to 8MB shared L2 cache memory in a cluster. The Vector Processing Unit (VPU) of the AX45MPV implements RISC-V Vector Extension (RVV) version 1.0. It supports configurations of up to 1024-bit vector width (VLEN) and datapath width (DLEN). The AX45MPV is excellent for computations involving large arrays of data such as computer vision, digital signal processing, image processing, machine/deep learning, and scientific computing.

Figure 1: Invoking SIM-V with the AX45MPV configuration.

“We are delighted to join forces with Andes to support the AX45MPV processor in SIM-V,” said Lukas Jünger, Managing Director at MachineWare. “The incorporation of the AX45MPV model enables our common customers to develop RISC-V Linux and AI software stacks and verify their functionality in minutes. This will eliminate bugs and elevate software quality all the while making the overall development process more efficient.”

“Andes’ collaboration with MachineWare is consistent with our continuous effort to broaden RISC-V ecosystem for easy adoption of high-performance simulation tools,” said Samuel Chiang, deputy marketing director of Andes Technology. “We are excited to come together with MachineWare to drive the expansion of the RISC-V ecosystem. And we believe RISC-V’s instruction set architecture will increase innovation and has the potential to transform the AI market.”

About MachineWare GmbH
Founded in 2022 in Aachen, Germany, MachineWare leverages decades of experience in system level simulation and high-performance simulation tooling. Visit https://www.machineware.de/ for more details.

About Andes Technology
Nineteen years in business and a Founding Premier member of RISC-V International, Andes is a publicly-listed company (TWSE: 6533; SIN: US03420C2089; ISIN: US03420C1099) and a leading supplier of high-performance/low-power 32/64-bit embedded processor IP solutions. Its V5 RISC-V CPU families range from tiny 32-bit cores to advanced 64-bit Out-of-Order processors with DSP, FPU, Vector, Linux, superscalar, automotive and/or multi/many-core capabilities. By the end of 2023, the cumulative volume of Andes-Embedded™ SoCs has surpassed 14 billion. For more information, please visit https://www.andestech.com . Follow Andes on LinkedIn, Twitter, Bilibili and YouTube!

About ANDES RISC-V CON
ANDES RISC- V CON is the annual RISC-V technology forum of Andes Technology. In 2024, the Hsinchu session will be held at Amazing Hall Yufeng on March 28; the Shanghai session will be held at DoubleTree by Hilton Hotel Shanghai – Pudong on April 9; the Shenzhen session will be held at Grand Mercure Shenzhen Oriental Ginza Hotel on April 11. The theme of this year is “ANDES RISC-V CON: Deep Dive into Automotive/ AI/ Application Processors and Security Trends.” It will introduce the flexible RISC-V that revolutionizes emerging applications and share Andes latest breakthroughs and innovations in RISC-V. Four popular applications will be focused on: AI, automotive electronics, security and RISC-V’s new field, application processor. Many RISC-V ecosystem partners, including TSMC, are invited to deliver talks and on-site demonstrations.

For more event details and free registration, please visit the official website of the events:

About RISC-V
The RISC-V open architecture ISA is under the governance of RISC-V International. Visit https://riscv.org for more details.


MachineWare Contact
Lukas Jünger, Managing Director
E-mail: lukas@mwa.re

Andes Technology Contact
Jonah McLeod, Press Contact, Andes Technology
Tel: +1-510-449-8634
E-mail: Jonahm@andestech.com

Continue ReadingAndes and MachineWare Collaborate on Early RISC-V Software Development for AndesCore™ AX45MPV