Read more about the article Seven Years of Uninterrupted Growth: Andes Technology Achieves Milestone Annual Revenue Exceeding NT$1 Billion

Seven Years of Uninterrupted Growth: Andes Technology Achieves Milestone Annual Revenue Exceeding NT$1 Billion

Andes Technology Is the No. 1 Provider of RISC-V CPU IP According to the SHD Marketing Report

【 Mar. 21, 2024 – Hsinchu, Taiwan】Since its IPO in 2017, Andes Technology (TWSE:6533) has established itself as a leader in the CPU IP sector, achieving a fivefold increase in sales over the past seven years. Andes has invested capital and R&D manpower to accelerate the launch of high-end products to ensure long-term competitiveness and maintain market leadership. It is expected that a competitive product portfolio will create the next wave of revenue peaks.

SHD report

(Image Source: SHD 2024 RISC-V Market Analysis)

With close monitoring of market dynamics and technology trends and decisive decision-making, Andes has strategically positioned the company to adeptly navigate challenges and seize emerging opportunities, such as bringing innovations in its proprietary AndeStar™ V3 ISA to the RISC-V based AndeStar™ V5 ISA in 2016. In 2023, even when the whole industry was still under inventory pressure, Andes surpassed a significant total shipment milestone of 14 billion Andes-Embedded™ SoCs. According to the SHD marketing report released on Jan 2024, Andes has secured an impressive 30% market share of RISC-V based chip shipping volume through its worldwide customers and is the number one provider of RISC-V CPU IP.

In 2023, the diverse product portfolio offered by Andes has resonated exceptionally well with the market and enabled its sustained growth. Andes has successfully launched the groundbreaking vector processor-AX45MPV, and the industry-revolutionizing automotive ISO 26262 fully certified core N25F-SE. More recently, Andes ventured into the application processor market with the launch of its cutting-edge out-of-order (OOO) processor AX65. AndesCore™ D23 and N225 are also released for the compact, performant, and secure applications. Besides the CPU IPs, Andes has also established a new product line, AndesAIRE™ or Andes AI Runs Everywhere, which offers a comprehensive hardware and software solution designed for edge and end-point inference.

Andes’s unwavering commitment to customer satisfaction has fostered robust relationships with its customers and fortified its market position. The addressable market segments of Andes products span a wide spectrum, encompassing AI/ML, 5G communications, FPGAs, image processing, IoT, MCU/MPU, sensors, storage, TDDI, and wireless connectivity.

Looking ahead, Andes would continue its dedication to innovations, customer satisfaction, and continual adaptation in the dynamic CPU IP licensing market. Below are a set of key drivers underpinning Andes’ growth:

Expansion of AI and HPC Applications: The ongoing surge in demand for AI and High-Performance Computing (HPC) applications, coupled with the requirements for specialized SoC, serves as one of the primary catalysts for Andes. Offering processors enhanced with ACE™ (Andes Automated Custom Extension) to meet the stringent requirements of AI and HPC workloads has significantly contributed to Andes’ market growth.

Increasing Demands for Automotive-Grade (ISO 262626) SoC: As the automotive industry continues to advance, there is a rising need for Automotive-Grade SoCs compliant with the ISO 262626 standard. Andes has seized this trend and is actively catering to the increasing demands for automotive-grade solutions. By offering processors designed to meet the stringent safety and reliability requirements of the automotive sector, Andes is well-positioned to capitalize on this growing market segment, further enhancing its success and market penetration.

Maturity of the RISC-V Ecosystem: By actively participating in the RISC-V International and community with the highest RVI membership and Summit sponsorship, Andes contributes to the RISC-V ecosystem’s fast expansion. Through this effort, Andes remains at the forefront of RISC-V development, fostering a positive cycle benefiting both the company and the ecosystem.

Rise of Multi-Core Heterogeneous SoC: The growing complexity of modern applications, spanning various domains like AIoT, edge computing, and data centers, has led to the rise in multi-core heterogeneous System-on-Chips (SoCs). Andes’ strategic focus on developing a diverse product portfolio aligns seamlessly with the demands of multi-core heterogeneous SoCs. These processors offer the performance and flexibility needed to address the contemporary applications’ requirements.

“Andes Technology’s journey of consistent growth over the past seven years is a testimony to our unwavering determination of staying ahead of industry trends and commitment to customers,” said Frankwell Lin, the Chairman, and CEO of Andes Technology. “We remain dedicated to shaping the future of the CPU IP licensing market with cutting-edge solutions.”

“As Andes charts our roadmap for the future, with ‘Driving Innovations’ as our motto, on one hand, we are developing high-end products that push the boundaries of performance,” remarked Dr. Charlie Su, the CTO and President. “On the other hand, we continue to deliver strong compact processors for power-efficiency and security. Aligning our expertise with the evolving needs of this dynamic industry, our talented team and effective collaboration with customers will continue to drive us forward, shaping the future of high-performance and high-efficiency computing, complying to strict safety demands in automotive SoC, and addressing the ever-emerging AI requirements.”

 About ANDES RISC-V CON

ANDES RISC- V CON is the annual RISC-V technology forum hosted by Andes Technology and sponsored by partners. In 2024, the San Jose session will be held in Doubletree by Hilton Hotel on June 11. The 2024 theme is “Deep Dive into Automotive/AI/Application Processing and Security Trends.” It will introduce the flexible RISC-V processors that changes the face of emerging computing and share how Andes assists the RISC-V ecosystem in implementing diversified applications of innovative technologies. Four popular application areas will be focused on: AI/ML, automotive electronics, application processing and security. Many ecosystem partners are invited to give talks and on-site demonstrations. For free registration, please see the official website of Andes RISC-V CON https://www.andestech.com/Andes_RISC-V_CON_2024_US/

About Andes Technology

Nineteen years in business and a Founding Premier member of RISC-V International, Andes is a publicly-listed company (TWSE: 6533; SIN: US03420C2089; ISIN: US03420C1099), a leading supplier of high-performance/ low-power 32/64-bit embedded processor IP solutions, and the driving force in taking RISC-V mainstream. Andes’ fifth-generation AndeStar™ architecture adopted the RISC-V as the base. Its V5 RISC-V CPU families range from tiny 32-bit cores to advanced 64-bit Out-of-Order processors with DSP, FPU, Vector, Linux, superscalar, functional safety, and/or multicore capabilities. By the end of 2023, the cumulative volume of Andes-Embedded™ SoCs has surpassed 14 billion. For more information, please visit https://www.andestech.com. Follow Andes on LinkedIn, Facebook, X, Bilibili and YouTube! 

 

Continue ReadingSeven Years of Uninterrupted Growth: Andes Technology Achieves Milestone Annual Revenue Exceeding NT$1 Billion

Andes Technology Showcases Pioneering RISC-V CPU IP Solutions at RISC-V Summit Europe

 Discover the Future of CPU Technology and the RISE project at Andes’ Exhibition Display in Booth 14

Barcelona, Spain – June 5, 2023 – Andes Technology Corporation (TWSE: 6533; SIN: US03420C2089; ISIN: US03420C1099), a leading provider of high efficiency, low-power 32/64-bit RISC-V processor cores and a Founding Premier member of RISC-V International, is pleased to announce its diamond sponsor participation in the prestigious RISC-V Summit Europe. This premier event, taking place from June 5 to 8, 2023 in Barcelona, Spain, will feature Andes as a key contributor, presenting a keynote speech, poster publication, and participation in an automotive panel discussion. Additionally, Andes will be showcasing its cutting-edge RISC-V CPU IP solutions at booth #14.

Join Dr. Charlie Su, President and CTO of Andes, as he delivers an engaging keynote titled “RISC-V is Firing on All Cylinders” on June 6 at 12:00 PM. Dr. Su will highlight the rapid adoption of RISC-V across a wide range of applications, from small microcontrollers to AI/ML accelerator systems in data centers. The keynote will provide examples of RISC-V applications and the corresponding solutions to support them and will also explore different approaches for matrix multiplication extension, enabling direct AI/ML acceleration with the RISC-V architecture. Furthermore, Dr. Charlie Su will contribute to a panel discussion on “Automotive/Embedded” on June 6 at 17:30 PM. Andes recently announced its new product line, AndesAIRE™, which offers highly efficient AI/ML solutions for edge and end-point inference. On, June 7, Warren Chen, Andes senior Technical Manager, Marketing, will give a demo presentation titled “Andes AI Runs Everywhere (AndesAIRE™) with DSP/Vector/NN Libraries and AndesClarity” in the demo theater on June 7 at 11:10 AM.

In addition, Andes will proudly showcase development boards with AndesCore-Embedded™ technology at booth #14. These boards include the Tinker V, the first RISC-V Single-Board Computer (SBC) from ASUS IoT; an MPU development board from Renesas; an AI development kit with a camera module from Canaan; the IT9836 TDDI demo board from ITE; and the PC802SCB 5G small cell reference design from Picocom.

You can learn more about the RISC-V Software Ecosystem (RISE) project on Andes booth #14. “Andes is proud to be part of the newly launched RISE Project, a new open source initiative to accelerate the development of software for RISC-V across a variety of market segments. Hosted by Linux Foundation Europe, RISE will support the global standards activities and achievements of RISC-V International,” said Dr. Charlie Su, CTO and President of Andes Technology and a Director of the RISE Governing Board. Please visit the RISE website for how to join and other information.

This event presents a valuable opportunity for RISC-V enthusiasts to engage in one-on-one discussions with Andes experts, enabling deeper exploration of RISC-V solutions. We invite you to visit booth #14 at the RISC-V Summit Europe and experience live demonstrations of our leading-edge CPU IP technology.

Details of Andes’ sessions during the RISC-V Summit Europe are as follows:

Tuesday, June 6,

  • 12:00 – 12:15 PM: Keynote “RISC-V is Firing on All Cylinders” by Dr. Charlie Su, President and CTO
  • 17:30 – 18:30 PM: Automotive/Embedded Panel by Dr. Charlie Su, President and CTO

Wednesday, June 7,

  • 11:10 – 11:30 AM: Demo Talk “Andes AI Runs Everywhere with DSP/ Vector/ NN Libraries and AndesClarity” by Warren Chen, Senior Technical Manager, Marketing

For more information, please visit the RISC-V Summit Europe website.

About Andes RISC-V CON
Andes RISC- V CON is the annual RISC-V technology forum of Andes Technology. In 2023, the San Jose session will be held in Doubletree By Hilton Hotel on June 27. The 2023 theme is “RISC-V: Redefining AI’s Future In Automotive, Data Center, Communications, And IoT”. It will introduce the flexible RISC-V that changes the face of emerging computing and share how Andes assists the RISC-V ecosystem in implementing multiple applications of innovative technology. Three popular application areas will be focused on: AI, automotive electronics, and RISC-V’s new field, Android. Many RISC-V ecosystem partners, including TSMC, are invited to give talks and on-site demonstrations. For free registration, please see the official website of Andes RISC-V CON: https://www.andestech.com/Andes_RISC-V_CON_2023_US/

About Andes Technology

Eighteen years in business and a Founding Premier member of RISC-V International, Andes is a publicly-listed company (TWSE: 6533; SIN: US03420C2089; ISIN: US03420C1099), a leading supplier of high-performance/ low-power 32/64-bit embedded processor IP solutions, and the driving force in taking RISC-V mainstream. Andes’ fifth-generation AndeStar™ architecture adopted the RISC-V as the base. Its V5 RISC-V CPU families range from tiny 32-bit cores to advanced 64-bit Out-of-Order processors with DSP, FPU, Vector, Linux, superscalar, and/or multi/many-core capabilities. By the end of 2022, the cumulative volume of Andes-Embedded™ SoCs has surpassed 12 billion. For more information, please visit https://www.andestech.com. Follow Andes on LinkedIn、Facebook、Weibo、Twitter、Bilibili and YouTube! 


Continue ReadingAndes Technology Showcases Pioneering RISC-V CPU IP Solutions at RISC-V Summit Europe

Ashling RiscFree™ now supports Andes Technology RISC-V CPUs

San Francisco, California – December 6, 2021 – RISC-V Summit 2021. Ashling and Andes Technology announced today that Ashling’s RiscFree™ Toolchain will be extended to support the broad range of Andes RISC-V CPU IPs including support for the AndeStar™ V5 Performance and CoDense™ ISA Extension.

RiscFree™ is Ashling’s Integrated Development Environment (IDE), Compiler and Debugger for RISC-V based development and now adds support for Andes RISC-V CPUs including the 32-bit: N22, N25F, D25F, A25, A25MP, A27, A27L2, N45, D45, A45 & A45MP and the 64-bit: NX25F, AX25, AX25MP, NX27V, AX27, AX27L2, NX45, AX45 & AX45MP.
“Ashling’s RiscFree™ with its Different Cores, One Solution feature set now brings the power of heterogeneous, multi-core debugging to Andes RISC-V CPU users allowing a single instance of RiscFree™ to debug any number of heterogeneous and homogeneous cores” said Hugh O’Keeffe, Managing Director of Ashling.

“We are delighted to have Ashling RiscFree™ support Andes RISC-V CPU cores and offer an additional choice for our customers, particularly those working on heterogeneous SoC designs utilizing AndesCore™ V5 RISC-V processors with increased performance and reduced code size” said Dr. Charlie Su, Andes Technology President and CTO.
For more information on Ashling’s RiscFree™ see: https://www.ashling.com/ashling-riscv/ and for details on Andes RISC-V CPU cores see: http://www.andestech.com/en/products-solutions/andescore-processors/.

Ashling_Andes

About Ashling
Ashling have been a leading provider of Embedded Development Tools & Services since 1982 with design centres in Limerick Ireland and Chennai India and sales and support offices in Europe, Asia Pacific, the Middle East and America. We have over thirty years’ experience in developing tools for embedded systems engineers including high-speed Debug and Trace Probes supporting a broad range of MCUs, SoCs and Soft (FPGA) based designs. Our software tools include IDEs, Debuggers, Compilers and Simulators and we support all the main embedded architectures including ARC, Arm, MIPS, Power Architecture and RISC-V through our RiscFree™ platform. We have a particular focus on RISC-V and are the first company to bring tools to the market supporting heterogenous debug of RISC-V cores along with cores from other vendors. Visit www.ashling.com for more details.
Contact Nadim Shehayed: nadim@ashling.com

About Andes Technology
Sixteen years in business and a Founding Premier member of RISC-V International, Andes is a leading supplier of high-performance/low-power 32/64-bit embedded processor IP solutions, and the driving force in taking RISC-V mainstream. Andes’ fifth-generation AndeStar™ architecture adopted the RISC-V as the base. Its V5 RISC-V CPU families range from tiny 32-bit cores to advanced 64-bit cores with DSP, FPU, Vector, Linux, superscalar, and/or multicore capabilities. The annual volume of Andes-Embedded SoCs has exceeded 2 billion since 2020 and continues to rise. At the end of Q3 2021, the cumulative volume of Andes-Embedded™ SoCs has reached 9 billion. For more information, please visit https://www.andestech.com. Follow Andes on LinkedIn, Twitter, Facebook, and YouTube! 
Contact Hsiao-Ling Lin: hllin@andestech.com 

About RISC-V
The RISC-V open architecture ISA is under the governance of the RISC-V International. Visit https://riscv.org for more details

Continue ReadingAshling RiscFree™ now supports Andes Technology RISC-V CPUs

Codeplay Software partners with Andes Technology to achieve Software First SoC Design for AI-based applications using RISC-V Vector Processors

Codeplay’s Acoran Software Platform adds support for AndesCore™ NX27V.

San Francisco, California – December 6, 2021 – Codeplay Software®, the industry leader and pioneer in Open-Standard software tools and services for artificial intelligence, machine-learning, and high-performance computing announced support for Andes Technology Corporation’s AndesCore™ NX27V IP. Andes Technology is a leader in high-performance / low-power IP and a founding premier member of RISC-V International. The NX27V is an RV64GC vector processor supporting the RISC-V Vector specification with up to 512-bit VLEN and SIMD width (or DLEN). It allows SoC designers to create next-generation compute-acceleration solutions that leverage AI, ML, and HPC in both the edge and the cloud. Initially, Codeplay will deliver support through the AndesCore performance simulator that provides near cycle accurate information. This will enable customers to implement a software-first strategy and then move to specific SoC architecture based on the NX27V.
Compute-accelerated solutions need a new programming model to leverage all the capabilities of the processing power available. Incorporating one or more vector processor cores, SoC developers and designers can create applications that leverage a Single-Instruction / Multi Data (SIMD) heterogeneous architecture. Artificial Intelligence and Machine Learning applications are required to process a significant amount of vector data for applications like neural networks and computer-vision algorithms seen in cloud acceleration cards, autonomous vehicles and visual recognition. A powerful vector processor like the NX27V can rapidly increase the performance of processing this data.
Coldplay’s Acoran software platform support for NX27V-based simulator and then SoC will provide a wide ecosystem of domain-specific optimized libraries for exascale and artificial intelligence. A key foundation of Acoran is SYCL, an open standard programming model that enables heterogeneous programming based on standard ISO C++.
“The NX27V has been adopted by about 10 customer SoC projects for the datacenter accelerators. All incorporate multiple instances of our vector processor in cluster-based heterogenous architecture,” said Dr. Charlie Su, President and CTO at Andes Technology. “The exciting partnership with Codeplay enables us to bring elegant programming solutions to our customers. We are at the beginning of the next wave SoCs with Domain-Specific Architecture (DSA) for applications ranging from embedded devices to datacenter accelerators that support AI and HPC. The growth potential in this area is enormous.”
“Codeplay is embracing the software-first approach to designing complex compute systems,” said Andrew Richards, CEO and founder of Codeplay Software. “This partnership with Andes will bring developers of RISC-V vector SoCs the opportunity to optimize their architecture based on real application software.”
“Collaboration is at the heart of the RISC-V ecosystem, so it’s great to see members join forces to develop innovative new approaches for the benefit of the entire community,” said Calista Redmond, CEO of RISC-V International. “Together, Andes Technology and Codeplay Software are offering a solution to allow developers and designers to leverage the best of open standards for hardware and software.”
“SYCL has been adopted by organizations building large supercomputers with a variety of GPU architectures. This partnership will help to bring open standard programming to the next generation of specialist processors implementing the RISC-V ISA, which is very exciting for hardware and software developers,” said Michael Wong, Chair of SYCL Working Group within The Khronos Group, Chair of Datacenter / Cloud Computing SIG with RISC-V International, and Distinguished Engineer at Codeplay Software.
Codeplay and Andes welcome companies looking to embrace RVV for accelerating their AI systems to evaluate the solution.

Codeplay_Andes

About Andes Technology
Sixteen years in business and a Founding Premier member of RISC-V International, Andes Technology (TWSE: 6533; SIN: US03420C2089; ISIN: US03420C1099) is a leading supplier of high-performance/low-power 32/64-bit embedded processor IP solutions, and the driving force in taking RISC-V mainstream. Andes’ fifth-generation AndeStar™ architecture adopted the RISC-V as the base. Its V5 RISC-V CPU families range from tiny 32-bit cores to advanced 64-bit cores with DSP, FPU, Vector, Linux, superscalar, and/or multicore capabilities. The annual volume of Andes-Embedded SoCs has exceeded 2 billion since 2020 and continues to rise. At the end of Q3 2021, the cumulative volume of Andes-Embedded™ SoCs has reached 9 billion. For more information, please visit https://www.andestech.com. Follow Andes on LinkedIn, Twitter, Facebook, and YouTube! 

About Codeplay Software
Codeplay Software is a world pioneer in enabling acceleration technologies used in AI, HPC and automotive. Codeplay was established in 2002 in Edinburgh, Scotland and developed some of the first tools enabling complex software to be accelerated using graphics processors. Today, most AI software is developed using graphics processors designed for video games, and more recently specialized AI and computer vision accelerators. Codeplay continues to work with global technology leaders to make the latest complex AI systems programmable using open standards based programming languages and allows application developers to quickly bring software to the market. Codeplay is also deeply involved with the definition of open standards, especially OpenCL™, SPIR™, SYCL™, and Vulkan™ through The Khronos Group, and MISRA C++ for automotive.
SYCL, SPIR, Vulkan are trademarks of the Khronos Group Inc. OpenCL and the OpenCL logo are trademarks of Apple Inc. used by permission by Khronos.

For more information, please contact:
Charles Macfarlane
Chief Business Officer
Codeplay Software
charles.macfarlane@codeplay.com
+44 7766 104856

Continue ReadingCodeplay Software partners with Andes Technology to achieve Software First SoC Design for AI-based applications using RISC-V Vector Processors

Kneron Edge AI SoC Powered by Andes RISC-V Processor Core D25F

San Diego, CA, November 4, 2021 – Kneron Inc., the San Diego-based Edge AI solution provider, together with Andes Technology Corporation (TWSE: 6533; SIN: US03420C2089; ISIN: US03420C1099), a leading supplier of high-performance, low-power 32/64-bit RISC-V processor cores, today announced formal mass production of Kneron’s next-generation Edge AI SoC KL530, powered by Andes’ D25F processor in consideration of its efficient pipeline architecture, powerful Packed-SIMD DSP extension instructions, and IEEE754-compliant high-performance single/double precision floating RVFD extensions.

KL530 is the latest generation of heterogeneous AI chip from Kneron, with a brand new NPU architecture. It is the first of its kind in the industry to support INT4 precision and Transformer. Compared with other Edge AI chips, it has higher computing efficiency and lower power consumption. The use of heterogeneous AI chips embedded with RISC-V processors, powerful image processing capabilities and interfaces will further enable the application of Edge AI chips in ADAS, AIoT and other market.

The computing power of KL530 can reach 1 TOPS@INT 4, and the processing efficiency is up to 70% higher than that of INT 8 under the same hardware conditions. Its reconfigurable NPU design takes advantage of the high performance of the D25F RISC-V core, and supports multiple AI models such as CNN, Transformer, RNN Hybrid, etc. Its Smart ISP can optimize image quality based on AI, and powerful codec can achieve high-efficiency multimedia compression. In addition, its cold start time is less than 500ms, and average power consumption is less than 500mW.

The D25F CPU, one of the most popular cores from AndesCore™ 25-series, is equipped with RISC-V P-extension ISA draft to efficiently manipulate multiple data sets simultaneously in one instruction. Andes initiated the P-extension, chairs its Task Group in RISC-V International and leads the specification definition. D25F is accompanied with complete development tools including compiler with auto-generation of SIMD instructions based on vector data type, optimized DSP libraries, neural network libraries, and near cycle-accuracy simulator. It delivers near 9 times speedup for popular machine learning algorithms, including Tensorflow keyword spotting, CIFAR10 image classification, and P-net object detection.

“Kneron has a unique reconfigurable architecture, which can fit easily into different convolutional neural networks (CNN) without compromise, thus serves a wide variety of AI models seamlessly and accurately.” said Albert Liu, Kneron founder and CEO. “The D25F CPU core with its powerful DSP instruction set and development framework enables Kneron to explore the performance of its industry-leading AI algorithms to the fullest while keeping power consumption optimal. It is crucial to our customers, especially for those who develop products such as smart devices and Edge AI appliances. We are happy to cooperate with Andes, the leading computing expert specialized in RISC-V architecture. With Andes RISC-V core and its DSP support, Kneron is able to develop this cutting edge solution smoothly within a very short time frame. We are really proud to see KL530 in mass production now serving our customers.”

“We are glad that Kneron chose the D25F to power KL530, especially after it went through a series of comprehensive evaluations,” said Andes CEO and RISC-V International Board Director Frankwell Lin. “The D25F stands out distinctly in every aspect on key indexes such as product features, performance, core area, and power consumption. As a leading enterprise in providing Edge AI SoC solution embedded with RISC-V core, Kneron showed its efficiency to quickly launch KL530 and enter mass production. It is astonishing to learn the strong competitiveness of Kneron’s team. Thanks to the extraordinary cooperation between Kneron and Andes, we jointly achieved a complete and highly competitive solution to facilitate AI applications for a wide variety of products.”

Kneron KL530 Product Launch

Kneron KL530 online product launch conference will be held at 10:00-11:30 am, November 4th (PDT). GSA CEO Jodi Shelton, Winbond President Pei-Ming Chan, and YouTube Founder Steven Chan are invited to have talks to offer their perspective on the next-generation Edge AI. Registration information https://www.kneron.com/en/event-registration/ab29527e 

About Kneron

Kneron is a San Diego based technology company that was founded in 2015. It develops both hardware and software products, which are used in smart devices to run and power AI applications. Kneron is a single port of call for device manufacturers who want to integrate AI into their products. The products include hardware such as AI chips and software such as AI models, that device manufacturers can use in everything from autonomous cars, all the way down to a smart fridge, doorbell, or any Internet of Things device. Kneron primarily solves three main problems for smart devices running AI — security, energy and cost, thereby enabling AI everywhere and for everyone. Kneron’s solutions are reconfigurable, and will be as efficient at processing image and audio AI models in the future as they are now. It has raised over $100mn to date and is backed by Horizons Ventures, Alibaba, Qualcomm, Sequoia, and more. For further information about Kneron, please visit: http://www.kneron.com/about.php

About Andes Technology

Sixteen years in business and a Founding Premier member of RISC-V International, Andes is a leading supplier of high-performance/low-power 32/64-bit embedded processor IP solutions, and a main force to take RISC-V mainstream. Andes’ fifth-generation AndeStar™ architecture adopted the RISC-V as the base. Its V5 RISC-V CPU families range from tiny 32-bit cores to advanced 64-bit cores with DSP, FPU, Vector, Linux, superscalar, and/or multicore capabilities. The annual volume of Andes-Embedded SoCs has exceeded 2 billion since 2020 and continues to rise. To the end of 2020, the cumulative volume of Andes-Embedded™ SoCs has reached 7 billion. For more information, please visit https://www.andestech.com. Follow Andes on LinkedIn, Twitter, Facebook, and YouTube!

 

Continue ReadingKneron Edge AI SoC Powered by Andes RISC-V Processor Core D25F

Andes Technology USA Corp. Announces Major Expansion of Its U.S. Operation

Company Announces Job Openings for San Jose Headquarters and Portland R&D Office

San Jose, California October 8, 2021 – Andes Technology USA Corp., the headquarters of North America operations of Hsinchu, Taiwan-based Andes Technology Corporation, a leading supplier of high efficiency, low-power 32/64-bit RISC-V processor cores and founding premier member of RISC-V International, today announced a major expansion of Its U.S. operation. Andes Technology USA is greatly increasing engineering headcount in both the San Jose, California headquarters and its Portland, Oregon research and development facility. Andes Technology USA is seeking engineers in the U.S. and Canada to work remotely or in the Portland or San Jose offices. Openings are available for design engineers, verification engineers, and field application engineers.

Andes Technology USA Corp. was established in 2015 as a California corporation coincident with Andes Technology Corp. joining RISC-V International. After Andes took the RISC-V instruction set architecture (ISA) as the base to form its fifth generation architecture, AndeStar™ V5 and started developing V5 processor IP’s, the U.S. operation was formed to be nearby early customer adopters of the new ISA. The U.S. subsidiary established an R&D lab shortly thereafter and began developing architectures for the high-end RISC-V processors. In under a year the investment together with the main engineering team in Taiwan yielded the first commercial RISC-V Vector processor IP which won nearly 10 projects including datacenter projects from a large OEM so far.

“Major semiconductor companies worldwide adopting the RISC-V ISA and the RISC-V International work groups rapid development of the RISC-V ISA extensions is driving demand for engineers to keep up with the fast pace of new technology development,” said Emerson Hsiao, Andes Technology USA Corp. Chief Operating Officer. “RISC-V customers like the growing number of extensions coming available as well as their ability to customize the architecture to better fit their processing requirements. Our tool Andes Custom Extensions (ACE) makes the customization process easier and less risky. To keep up with RISC-V technical developments and to serve our customers’ requests, we expect to greatly expand the size of our U.S. operation.”

Engineers interested in Andes are encouraged to view the open positions on the Andes Technology LinkedIn page.

 

About Andes Technology USA Corp.
Andes Technology USA Corp. was formed as a California corporation in 2015 in San Jose California to develop high-end CPU architectures. Emerson Hsiao, Chief Operating Officer heads the office, located in the heart of Silicon Valley in San Jose. In June 2018, the U.S. operation added its R&D facility in Portland, Oregon to attract engineers in the Pacific Northwest and Canada. To date, the U.S. operation continues to develop new high-end CPU processor architecture. Its most significant achievement is the development of the first RISC-V vector architecture based on the RISC-V International RVV specification. Andes developed the first RISC-V vector architecture based on version V0.8 of the specification and has advanced it to the latest to-be-ratified version.

About Andes Technology
Sixteen years in business and a Founding Premier member of RISC-V International, Andes is a leading supplier of high-performance/low-power 32/64-bit embedded processor IP solutions, and a main force to take RISC-V mainstream. Andes’ fifth-generation architecture AndeStar™ adopted the RISC-V as the base. Its V5 RISC-V CPU families range from tiny 32-bit cores to advanced 64-bit cores with DSP, FPU, Vector, Linux, superscalar, and/or multicore capabilities. The annual volume of Andes-Embedded SoCs has exceeded 2 billion since 2020 and continues to rise. To the end of 2020, the cumulative volume of Andes-Embedded™ SoCs has surpassed 7 billion.

About RISC-V AndesCore™
Andes Technology’s comprehensive CPU includes entry-level, mid-range, high-end, extensible and security families to address the full range of embedded electronics products, especially for connected, smart and green applications. From 2017, Andes expands its product line to RISC-V processors and provides a total solution in V5 family cores, including N22, N25F/NX25F, D25F, A25/AX25, A25MP/AX25MP, A27/AX27/NX27V, A45/D45/N45, AX45/DX45/NX45 and A45MP/AX45MP.

For more information, please visit https://www.andestech.com. Follow Andes on LinkedIn, Twitter, Facebook, and YouTube!

Contact Information
Andes Technology –  hr@andestech.com

Continue ReadingAndes Technology USA Corp. Announces Major Expansion of Its U.S. Operation

Imperas updates Free reference model riscvOVPsimPlus with new RISC-V P (SIMD/DSP) extension and Architectural Validation Test Suites

Imperas simulation technology and reference model available for free, including test suites for basic processor hardware verification and compliance testing

Imperas press release on SIMD/DSP RISC-V P Extension

 

Oxford, United Kingdom, July 19th, 2021 — Imperas Software Ltd., the leader in RISC-V processor verification technology, announces the latest updates to riscvOVPsimPlus with support for the near ratified P extension and architectural validation test suites. The P (or Packed SIMD/DSP) extension is a significant addition to the flexibility of the modular RISC-V ISA (Instruction Set Architecture); it supports real-time data processing applications as part of the main processor pipeline without the need for the associated inefficiencies of a co-processor. For processor hardware verification, a basic test suite helps ensure implementations have a basic software level compatibility to the new P extension as a reference to the developers’ interpretation of the written specification.

riscvOVPsimPlus is a popular free ISS (Instruction Set Simulator) that is an envelope model that can be configured to cover all of the ratified RISC-V specifications and standard extensions. Also included are several Architectural Validation Test Suites, which form a basic test plan for software level compatibility within the specification definitions. The Imperas models are available as open- source and licensed under the Apache 2.0 flexible open-source license. All models, virtual platforms and example models are provided to the community via the Open Virtual Platforms website www.OVPworld.org. The Imperas commercial simulation technology and products are based on the freely available open-standard public OVP APIs.

The Imperas RISC-V architectural validation test suites are collections of tests focused on specific ISA extensions that provide basic testing of instruction execution and usage of the full range of operands with a set of representative data values. They are not a substitute for full detailed tests suites for design verification but provide detailed coverage reports of the different parts of the architectural specification tested. The currently released test suites available free on the OVP website now include P-SIMD/DSP, K-crypto, V-vector, B-bitmanip, F, D, I, M, and C.

“Flexibility within a framework of compatibility is the essential foundation of the RISC-V ISA,” said Chuanhua Chang, Andes Technology Corporation, Chair of RISC-V International P Extension Task Group. “The RISC-V P extension defines a rich set of integer SIMD/DSP instructions operating on existing integer registers to support complex data processing within the constraints of real-time applications. However, the hardware specification is just the start – adoption and success depend on the software ecosystem, which is supported with the reference models and test suites from Imperas.”

“By combining SIMD/DSP functionality within the RISC-V ISA offers the ideal balance for performance, flexibility and efficiency,” said Wei Wu, PLCT Lab, ISCAS, Vice-Chair of RISC-V International P Extension Task Group. “The Imperas RISC-V reference model provides the ideal starting point to explore and develop software algorithms based on the new RISC-V P extension.”

“The Imperas simulation technology and RISC-V reference models are in active use in some of the most complex RISC-V verification projects,” said Simon Davidmann, CEO at Imperas Software Ltd. “RISC-V is changing the design process as new design exploration can start without many of the traditional barriers. The adoption of riscvOVPsimPlus with the new RISC-V P extension support helps provide clarification of the specification boundary as a useful guideline for innovation in new processor designs.”

 

About RISC-V Processor Verification IP

The free riscvOVPsimPlus package including the test suites and functional coverage analysis are now available on OVPworld at www.ovpworld.org/riscvOVPsimPlus.The riscvOVPsimPlus solution is an entry ramp for development and verification and includes a proprietary freeware license from Imperas, which covers free commercial use as well as academic use. The simulator package also includes a complete open-source model licensed under the Apache 2.0 license.

The RISC-V processor Verification IP, example test benches and any customer-specific test suites are Imperas commercial solutions. Imperas also provides solutions for developers of more advanced RISC-V designs, who need multicore, or custom instruction support and advanced verification techniques. Imperas also offers a rich library of models for virtual platforms as used in early software development and hardware verification, including methodologies around continuous integration and regression using ‘virtual’ test farms, plus support for hybrid verification platforms with hardware emulators provided by Cadence Palladium, Siemens EDA Veloce, and Synopsys Zebu.

The Imperas simulation technology and reference models support the full spectrum of RISC-V processor verification requirements from a basic functional test, routine specification compliance, coverage driven verification, right through to the latest step-and-compare flows. The step-and- compare methods used for complex designs cover both asynchronous events and also, when integrated into a UVM SystemVerilog test bench, provide a seamless environment for efficient debug and analysis. To learn more about the options for RISC-V verification, visit www.imperas.com/riscv.

About Imperas

Imperas is the leading provider of RISC-V processor models, hardware design verification solutions, and virtual prototypes for software simulation. Imperas, along with Open Virtual Platforms (OVP), promotes open source model availability for a spectrum of processors, IP vendors, CPU architectures, system IP and reference platform models of processors and systems ranging from simple single core bare metal platforms to full heterogeneous multicore systems booting SMP Linux. All models are available from Imperas at www.imperas.com and the Open Virtual Platforms (OVP) website.

For more information about Imperas, please see www.imperas.com. Follow Imperas on LinkedIn, twitter @ImperasSoftware and YouTube.

 

Continue ReadingImperas updates Free reference model riscvOVPsimPlus with new RISC-V P (SIMD/DSP) extension and Architectural Validation Test Suites

Andes certifies Imperas RISC-V Reference Models for the new RISC-V P (SIMD/DSP) extension

Imperas simulation technology and RISC-V reference models updated to cover the RISC-V P Extension for SoC architecture exploration and early software development

Andes Certifies Imperas RISC-V Reference Models For The New RISC-V P (SIMD/DSP) Extension

Oxford, United Kingdom, July 12th, 2021 — Imperas Software Ltd., the leader in virtual platforms and high-performance software simulation, today announced that Andes Technology Corp., a leading supplier of performance-efficient and extensible 32/64-bit RISC-V CPU cores and a Founding Premier member of the RISC-V International Association, has certified the Imperas reference models for the complete range of Andes IP cores with the new RISC-V P extension. Developers can now use the Imperas reference models to evaluate multicore design configuration options for SoC architecture exploration.

The open standard RISC-V ISA (Instruction Set Architecture) has a modular structure based on multiple independent extensions that offer dedicated and enhanced functionality to optimize a processor for the target application. The new SIMD/DSP extension, designated as ‘P’ in the specification description, supports efficient data processing applications and real-time requirements. The RISC-V International P Extension Task Group is in the final stages of submitting the specification to the official ratification process, which is expected to be completed within H2 2021.

The Imperas simulation technology enables fast and accurate virtual platforms that are central to modern SoC design and embedded software development. Working with lead customers, the Imperas models of the Andes cores have already been used for commercial projects, which are now implemented in silicon.

Optimizing a multicore design is one of the most challenging design tasks. Multiple independent processing units interacting with each other plus shared peripherals together with real-time processing tasks supporting a mix of OS/RTOS running firmware and application software. SoC architecture exploration allows a full evaluation of software running before the final decision and configuration of the hardware options. These virtual prototypes also support early software development, often many months before silicon prototypes are available. For final software testing, a virtual platform allows the actual binary code to be verified with access and visibility not available in real hardware or without compromising the software under test with additional test code.

“RISC-V is more than an ISA specification, it is a framework of flexibility; the real value is in the extensions and options available for processor core implementations,” said Dr. Charlie Su, President and CTO at Andes Technology Corp. “The RISC-V P extension within the Andes cores addresses the key real-time requirements in SIMD/DSP computations for new markets in audio/speech, IoT, tinyML and edge devices. Together with the Andes certified Imperas reference models, SoC developers can explore the next generation domain-specific solutions.”

“Embedded development depends on the optimized balance between hardware resources and software applications,” said Simon Davidmann, CEO at Imperas Software Ltd. “With the Imperas golden reference models, developers can explore full software development for all the Andes cores, including the new RISC-V P extension and Andes ACE custom instructions.”


About Andes Technology
Sixteen years in business and a Founding Premier member of RISC-V International, Andes is a leading supplier of high-performance/low-power 32/64-bit embedded processor IP solutions, and a main force to take RISC-V mainstream. Andes’ fifth-generation AndeStar™ architecture adopted the RISC-V as the base. Its V5 RISC-V CPU families range from tiny 32-bit cores to advanced 64-bit cores with DSP, FPU, Vector, Linux, superscalar, and/or multicore capabilities. The annual volume of Andes-Embedded SoCs has exceeded 2 billion since 2020, and the cumulative volume has reached 7 billion. For more information, please visit https://www.andestech.com. Follow Andes on LinkedIn, Twitter, Facebook and YouTube!

About Imperas
Imperas is the leading provider of RISC-V processor models, hardware design verification solutions, and virtual prototypes for software simulation. Imperas, along with Open Virtual Platforms (OVP), promotes open source model availability for a spectrum of processors, IP vendors, CPU architectures, system IP and reference platform models of processors and systems ranging from simple single core bare metal platforms to full heterogeneous multicore systems booting SMP Linux. All models are available from Imperas at www.imperas.com and the Open Virtual Platforms (OVP) website.

For more information about Imperas, please see www.imperas.com. Follow Imperas on LinkedIn, twitter @ImperasSoftware and YouTube.

Continue ReadingAndes certifies Imperas RISC-V Reference Models for the new RISC-V P (SIMD/DSP) extension

AndesBoardFarm Enables SoC Designers to Explore RISC-V Processors in Online FPGA Board Collection

HSINCHU, TAIWAN – June 9, 2021 – Andes Technology Corporation (TWSE: 6533), a leading supplier of high efficiency, low-power 32/64-bit RISC-V processor cores and founding premier member of RISC-V International, today announced “AndesBoardFarm”, a collection of on-line accessible FPGA boards and management software for SoC designers to experience the AndesCore™ RISC-V processors remotely from their local sites. By using the comprehensive AndeSight™ integrated development environment provided by Andes, designers can interactively try out their own software on Andes’ latest CPU cores over the internet to experiment on the performance test and get the results directly; at the same time, they can also explore the various hardware and software features offered by Andes. By taking advantage of the AndesBoardFarm services, the time and efforts for evaluating RISC-V processors will be greatly reduced, and designers will be able to pinpoint the best RISC-V CPU(s) for their SoCs with confidence.

“Creating a complex SoC with many RISC-V cores and developing applications to fully exploit the hardware features concurrently is a complex undertaking,” said Dr. Charlie Su, President and CTO of Andes Technology Corp. “Facing all the dynamics due to design complexity and fast changing requirements, it takes great visions to decide and secure the IPs that are most advantageous to their projects. To assist SoC design teams to determine the most suitable AndesCores from their own perspectives, Andes Technology created a collection of FPGA boards connected to a secure server complex and implemented secure management software. Customers can apply for an account and upload their program to an available board on the AndesBoardFarm site to save the efforts to work toward concluding their needs.” 

AndesBoardFarm FPGA boards accommodate all Andes RISC-V offerings embedded in reference SoC designs, including 32-bit and 64-bit processors with a single core or multi-core, and optional features such as MMU for Linux application, SIMD instructions for multimedia processing and vector extensions for AI and other complex computations with large volume of data.  For more information, please contact sales@andestech.com.

AndesBoardFarm

About Andes Technology
Andes Technology (TWSE: 6533) was established in Hsinchu Science Park in 2005. Sixteen years in business and a founding Premier member of RISC-V International, Andes is a leading supplier of high-performance/low-power 32/64-bit embedded processor IP solutions, and a main force to take RISC-V mainstream. Andes’ fifth-generation AndeStar™ architecture (V5) adopted the RISC-V as the base. Its V5 RISC-V CPU families range from tiny 32-bit cores to advanced 64-bit cores with DSP, FPU, Vector, Linux, superscalar and/or multicore capabilities. The annual volume of Andes-Embedded SoCs has exceeded 2 billion since 2020 and continues to rise. To the end of 2020, the cumulative volume of Andes-Embedded™ SoCs has surpassed 7 billion.

About RISC-V AndesCore™
Andes Technology’s comprehensive CPU includes entry-level, mid-range, high-end, extensible and security families to address the full range of embedded electronics products, especially for connected, smart and green applications. From 2017, Andes expands its product line to RISC-V processors and provides a total solution in V5 family cores, including N22, N25F/NX25F, D25F, A25/AX25, A25MP/AX25MP, A27/AX27/NX27V, A45/D45/N45 and AX45/DX45/NX45.
For more information about Andes Technology, please visit: http://www.andestech.com/

Continue ReadingAndesBoardFarm Enables SoC Designers to Explore RISC-V Processors in Online FPGA Board Collection

Andes Announces the New Upgrade of AndeSight™ IDE v5.0: a comprehensive software solution to accelerate RISC-V AI and IoT developments

Press Highlights:

  • AndeSight™ IDE v5.0 is to be released in mid-2021
  • Highlights of its features for AI and IoT applications include software solutions for RISC-V DSP/SIMD and Vector extension; Andes Neural Network (NN) Library; AndesClarity™ processor pipeline analyzer; debugging automation and scripting; multicore debugging; Linux LTS v5.4; and FreeRTOS and Zephyr

HSINCHU CITY, TAIWAN – April 23, 2021 –Andes Technology Corporation (TWSE: 6533), a leading supplier of high efficiency, low-power 32/64-bit RISC-V processor cores and Founding Premier member of RISC-V International, today announced the new upgrade of AndeSight™ IDE v5.0, which targets to accelerate RISC-V AI and IoT developments by strengthening several innovative and useful features.

AI and IoT applications are blooming everywhere. The products serving the market must not only come with good performance, high efficiency, and low power consumption to meet the constraints for computing and energy, but also need to reduce time-to-market to respond to the ever-changing market needs. AndeSight™  IDE v5.0 rolls out new functions to address those issues, and brings the ultimate runtime performance and development efficiency to users.

The Core for AI Computations: RISC-V DSP/SIMD extension (RVP), vector extensions (RVV), and the tools and runtime from AndeSight™ IDE

RVP exactly addresses the balance between low-volume data computation and power consumption. By providing the compact SIMD (Single Instruction Multiple Data) and DSP (Digital signal processing) capability, it forms a very competitive basis for the TinyML, AIoT, and signal processing applications on edge and endpoints. RVV targets high-volume data computation, no matter in the edge or cloud, it provides very scalable, efficient, and powerful compute capabilities for general AI, NN, and data processing applications.

To unlock the potential of a powerful ISA extension, a simple and straightforward programming model is critical. AndeSight™ IDE v5.0 supports toolchains for the standard-bound specification of RVP and RVV, highly-optimized DSP and Vector libraries, intrinsic functions, and sample codes to guide code optimization. A key advantage is that software developers can build applications completely in C using efficient intrinsic and optimized libraries APIs, freeing developers from writing error-prone assembly code, and matching the performance of the same applications built with hand-code assembly.

To explore the full capabilities of processors and achieve the ultimate performance, an advanced processor pipeline analyzer is needed. AndesClarity™ visualizes the performance and resource bottleneck. Stall bubbles and data dependency are shown clearly along with the instructions, the C source code, and hardware functional units.

In addition, Andes provides the “Andes NN Library” that dramatically speeds up the development of Neural Network algorithms. It achieves a 66x speedup of MobileNet-v1 with half-precision floating-point, 256-bit SIMD width, and 512-bit vector length over RISC-V baseline extension. Moreover, “TensorFlow Lite for Microcontroller” can execute all built-in NN models with Andes NN Library on development boards.

Develop Up-to-date RTOS and Linux Applications along with AndeSight™ IDE Powerful Tools

AndeSight™ IDE v5.0 supports Linux LTS (Long-Term Support) kernel v5.4, and the popular RTOS such as FreeRTOS and Zephyr. Andes Linux kernel has verified with LTP (Linux Test Project), and seamlessly booted with Fedora or Debian Linux distro on Andes development boards along with the device drivers. To provide a smaller image for embedded Linux applications, Andes also offers RISC-V 32-bit Linux kernel to run on the corresponding Andes processors. Andes FreeRTOS port has passed the “AWS Qualification Program for RTOS”, which validates the pre-integrated port on microcontroller-based boards by AWS (Amazon Web Service)1. Andes Zephyr port supports SMP (Symmetric Multi-Processing) and has been verified on Andes RISC-V multicore. Developers only need to focus on the application itself and do not need to worry about the fundamental software.

To further enhance the ultimate debugging efficiency, the versatile features of scripting and grouping are enabled by AndeSight™ IDE. AndeSight™ scripting can record the UI operations from one developer, and replay on another environment. It saves time to reproduce issues from the field. Similar to GDB Python scripts feature, users can automate and scale the debugging procedures with Python programming. “Core Grouping” is a useful feature to allow users to develop the multicore software with separate build and debug configurations, and sending debug commands to a specific set of cores at the same time.

AndeSight™ IDE v5.0 comprehensive features enriched from 16-year continuous development, including but not limited to the outstanding toolchains, highly-optimized C libraries, AndeSim™ near cycle simulator, easy-to-use profiling and analyzing tools, virtual hosting, RTOS awareness, and abundant reference codes.

“We are excited to announce that AndeSight™ IDE v5.0 is ready for release. AndeSight™ IDE v5.0 is the new milestone of our RISC-V software solutions. It is the latest Andes offering for RISC-V community, and we expect it to speed up RISC-V SoC development to a new level.” said Andes President and CTO Dr. Charlie Su. “Comprehensively optimized tools and runtime are the other sides of a coin. Processors cannot work efficiently and perform outstandingly without matching software solutions. We’ll continue to invest in our RISC-V software solutions to bring the best performance for RISC-V processor solutions to the RISC-V community.”

AndeSight™ IDE v5.0 will be available for licensing after June 2021. For more details of the AndeSight™ features, please visit Andes Webinar (http://www.andestech.com/en/webinar_en/) and register the talk “Accelerating RISC-V AI and IoT Development with Andes Software Solutions” at 10:00 AM (CEST) and 09:00 AM (PDT) in Arp 28 (Thu.).

 

About Andes Technology
Andes Technology (TWSE: 6533) was established in Hsinchu Science Park in 2005. Sixteen years in business and a founding Premier member of RISC-V International, Andes is a leading supplier of high-performance/low-power 32/64-bit embedded processor IP solutions, and a main force to take RISC-V mainstream. Andes’ fifth-generation AndeStar™ architecture adopted the RISC-V as the base. Its V5 RISC-V CPU families range from tiny 32-bit cores to advanced 64-bit cores with DSP, FPU, Vector, Linux, superscalar and/or multicore capabilities. The annual volume of Andes-Embedded SoCs has exceeded 2 billion since 2020. Up to the end of 2020, the cumulative volume of Andes-Embedded™ SoCs has reached 6 billion.

About RISC-V AndesCore™
Andes Technology’s comprehensive CPU includes entry-level, mid-range, high-end, extensible and security families to address the full range of embedded electronics products, especially for connected, smart and green applications. From 2017, Andes expands its product line to RISC-V processors and provides a total solution in V5 family cores, including N22, N25F/NX25F, D25F, A25/AX25, A25MP/AX25MP, A27/AX27/NX27V, A45/D45/N45 and AX45/DX45/NX45.

For more information about Andes Technology, please visit http://www.andestech.com/

 1: https://devices.amazonaws.com/detail/a3G0h0000077Y9QEAU/Corvette-F1-N25

Continue ReadingAndes Announces the New Upgrade of AndeSight™ IDE v5.0: a comprehensive software solution to accelerate RISC-V AI and IoT developments