Andes RISC-V Vector Processor NX27V is Upgraded to RVV 1.0
SAN JOSE, CA – December 02, 2020 – Andes Technology Corporation (TWSE: 6533), a leading supplier of high efficiency, low-power 32/64-bit RISC-V processor cores and Founding Premier member of RISC-V International, today announces the first commercial RISC-V vector processor IP, AndesCore™ NX27V, is upgraded to support the latest RISC-V Vector (RVV) extension spec (version 1.0), and several key features. RVV 1.0 includes new instructions such as vector floating-point reciprocal and reciprocal square-root estimate for math calculation. In addition to the existing register grouping, LMUL (vector length multiplier) adds fractional options to use less register bits to make it more flexible. The NX27V with powerful vector processing and parallel execution capability targets for the applications with large volumes of data such as AI, AR/VR, computer vision, cryptography, and multimedia.
The NX27V was designed from ground up to be a Cray-like full vector compute engine. Its Vector Registers are as wide as 512 bits each and can be extended to 4,096 bits through LMUL setting. It supports RVV standard data types such as integer, fixed point, and floating-point as well as Andes-enhanced data types optimized for AI representations. The NX27V contains a scalar unit and an Out-of-Order Vector Processing Unit (VPU). The latter has multiple functional units, operating simultaneously to generate up to 512-bit results every cycle to sustain the computation throughput needed in diversified applications. The NX27V comes with standard development tools and RVV compute libraries as well as AndesClarity™, a powerful visualization and analysis tool to help analyze and optimize the performance of critical computation kernels. Furthermore, OpenCL™ with integrated LLVM compiler is provided to enable parallel programming on heterogeneous computing architecture using multiple NX27V. With the configuration of 512-bit VLEN and SIMD width, the NX27V can achieve over 26x speedup in MobileNet v1, a popular convolution neural network (CNN).
Streaming Port is one of NX27V’s unique features based on ACE (Andes Custom Extension™) framework. It is a dedicated interface to efficiently exchange large amount of data between NX27V registers and an external module, which can range from a simple intelligent local memory to a full-featured DMA-capable hardware engine. The Streaming Port has decoupled command and data channels with an efficient handshaking protocol. As an example, ACE vector load/store instructions can be designed to send the control information to the command channel every cycle to enable a new vector data movement via the data channel while performing address increment and wraparound in parallel. Like RVV load/store instructions, they are aware of RVV controls such as LMUL. ACE vector load/store instructions respect data dependency because NX27V registers are scoreboarded. With the powerful Streaming Port, the NX27V can tightly interact with a hardware engine to fully exploit the efficiency of dedicated functions while leveraging the flexibility of comprehensive RVV extension to raise the overall performance.
“The NX27V has already been adopted by server-bound customers. In this release, it is upgraded to the latest RVV spec as well as the full ranges of data types up to 64 bits of FP64 and Int64. Its additional configurations of 256-bit VLEN and SIMD width extend NX27V’s coverage to a wider variety of requirements on performance and area,” said Andes CTO and EVP Dr. Charlie Su. “Together with the complete software development environment, the compute libraries and AI compiler support, NX27V is ready to take on high data rate applications from edge to cloud.”
“I am happy to announce that the NX27V was selected as a winner of 2020 ASPENCORE World Electronics Achievement Awards in the prestigious category of Outstanding Product Performance of the Year,” said Andes President Frankwell Lin. “I may be biased when I say the NX27V is the best vector processor IP, but winning the award evidently shows the international recognition of its excellent performance and rich features.”
NX27V is available for licensing now. Visit http://www.andestech.com/ for details or contact Andes sales at sales@andestech.com for more information.
Andes Announces New RISC-V Processors: Superscalar 45-Series with Multi-core Support and 27-Series with Level-2 Cache Controller
Hsinchu, Taiwan – November 30, 2020 – Andes Technology Corporation, the leader in RISC-V CPU solutions, today proudly announces new members of AndesCore™: high performance superscalar A45MP and AX45MP multicore processors, and A27L2 and AX27L2 processors with Level-2 (L2) cache controller.
The AndesCore™ 45-series IPs are in-order 8-stage dual-issue RISC-V processors, and equipped with optional DSP (RISC-V P-extension) unit, single or double precision Floating Point Unit and MMU (Memory Management Unit) that supports Linux-based applications as well. Its performance-efficient single core members, including 32-bit A45/D45/N45 and 64-bit AX45/NX45, have already been designed in by several customers since they are available last quarter. The new multi-core members, 32-bit A45MP and 64-bit AX45MP, support up to 4 cores with an optional L2 cache controller to meet the computing demands of heavy-duty applications such as AR/VR, AI/machine learning, 5G, In-Vehicle Infotainment (IVI), Advanced Driver Assistance Systems (ADAS), video/image processing, enterprise-grade storage device, and networking.
The newest members of the AndesCore™ 27-series, 32-bit A27L2 and 64-bit AX27L2, inherit the MemBoost feature, first made available in the 27-series, where multiple outstanding data accesses and I/D cache prefetch greatly boost the memory subsystem performance with higher bandwidth and lower access latencies. To bring the performance of memory-intensive applications to the next level, the L2 cache controller of the A27L2 and AX27L2 further raise memory bandwidth by 2x and reduce memory latencies by 70%.
“45MP processors are very important landmarks for Andes and RISC-V enthusiasts,” said Andes President, Frankwell Lin. “Our customers are looking to replace their high-performance application processors. It is exciting to see Andes RISC-V multi-core processors perfectly meet their expectations. Its directory-based coherence protocol allows the 45-series processors to support a larger multicore. In the meantime, we are happy to announce the availability of new members of 27-series, A27L2 and AX27L2. These two new cores provide an integrated L2 cache controller which makes them excellent for entry-level Linux-based applications requiring for the most power-efficient processor.”
“Multicore processors boost performance by using more cores and are suitable for applications with high parallelism. The 45MP supports up to four CPU cores with a Coherence Manager and an optional L2 cache controller. The Coherence Manager ensures cache coherence between Level-1 (L1) caches, the L2 cache, and cacheless bus masters, and help deliver efficient transactions for shared memory accesses,” said Dr. Charlie Su, CTO and Executive VP of Andes. “Compared with the single-issue 27-series processors, the well-designed dual-issue 45-series processors achieve more than 70% total performance enhancement with less than 50% additional logic area and dynamic power consumption. Furthermore, their maximum operating frequency can run up to 2.4 GHz at the popular 12nm process node,” Dr. Charlie Su further explained. “Similarly, the 27L2 processors with L2 cache controller and MemBoost are perfect for those designs that need only single core, but still require substantial performance on memory subsystem. The 45-series and 27-series together provide a wide spectrum of processor solutions to address diversified SoC requirements.”
All the new cores fully support Andes V5 architecture. Therefore, they are compliant with the most updated RISC-V extensions, and also all Andes V5 novel features such as PowerBrake, QuickNap™, and WFI for additional power saving; StackSafe™ for stack overflow/underflow protection; and CoDense™ for additional code density enhancement on top of RISC-V C-extension. Furthermore, the 45-series and 27-series processors benefit from all Andes development tools such as AndeSight™ IDE and Andes Custom Extension™ framework as well as RISC-V ecosystem from security solutions to system level modeling, and hardware debug/trace subsystems.
About Andes Technology
Fifteen years after starting from scratch, Andes Technology Corporation is now a world class creator of innovative high-performance/low-power 32/64-bit processor cores and associated development environment that serves the rapidly growing global market for embedded system applications. As a Founding Premier member of RISC-V International, Andes is the first mainstream CPU vendor that has adopted the RISC-V as the base of its fifth-generation architecture, the AndeStar™ V5. To meet the demanding requirements of today’s electronic devices, Andes delivers highly configurable and performance-efficient CPU cores with full-featured integrated development environment and comprehensive software/hardware solutions to help customers innovate their SoC in a shorter time to market. Since 2018, the yearly volume of SoCs Embedded with Andes CPUs has surpassed the 1-billion mark. Andes Technology’s comprehensive RISC-V CPU families range from the entry-level N22 (32-bit only), mid-range 25-series, advanced 27-series to high-performance superscalar 45-series.
For more information, please visit https://www.andestech.com
