Menta and Andes Announce Partnership Enabling Hardware Reconfiguring for ISA Extension

SOPHIA-ANTIPOLIS, FRANCE – December 7, 2020 – Menta S.A.S, a premier supplier of embedded FPGA (eFPGA) solutions, today announced a technology IP cooperation with Andes Technology, a founding premier member of RISC-V International and the leading supplier of 32/64bit RISC-V embedded CPU cores.

Andes is working with Menta to enable embedded programmable logic through eFPGA in its RISC-V AndesCore™ families. Menta and Andes share the same vision, providing customers with a joint solution that allows instruction set architecture (ISA) extension to be added or changed in the field.

Extending RISC-V ISA with custom instruction set extension, based on eFPGA co-extended core, is the key differentiator for the next processor unit’s generation. Designers will be able to add any instruction they need for the function that they want to accelerate, in the field. This is a powerful feature that does not break any software compatibility and leaves space for development and differentiation.

“It is an honour for Menta to work in close partnership with Andes Technology Corporation,” said Menta Chief Executive Officer Vincent Markus. “The innovative RISC-V ISA technology is open, compact, modular and extensible, making it a perfect fit for our eFPGA product line strategy.”

The eFPGA plays the role of a hardware co-extended core for the RISC-V CPU, unlocking the possibility to add or reconfigure ISA for the duration of the product’s life. Andes RISC-V processor families, already available in the SoC market as a mainstream computing engine, are now looking to enhance the product’s ACE (Andes Custom Extension™) feature by extending it with eFPGA hardware support.

ACE is a powerful framework to define new instructions on the Andes RISC-V processor cores. By writing ACE scripts for instruction semantics and concise Verilog for instruction execution register-transfer level (RTL), SoC designers can easily use Andes COPILOT (Custom-OPtimized Instruction deveLOpment Tools) to generate all required components automatically and extend the existing Andes processor package, including the processor RTL, compilation tools, debugger and cycle-accurate simulator, to support the new instructions to accelerate domain specific applications.

“By cooperating with Menta, we enable a brand new usage of Andes CPU cores to the market that embraces the characteristic of extensibility for the RISC-V ecosystem, especially in applications that require space for development and differentiation including AI and 5G,” said Chief Technology Officer and Executive Vice President of Andes Technology Dr. Charlie Su. “Customers can optimize and enrich their hardware with expected scale of cost by using Menta eFPGA solution to make reconfiguration of ACE custom instruction possible in post-silicon updates.”

The delivery of Menta pre-programmed eFPGA cores combined with the Andes RISC-V CPU cores will be provided with specialized user interface tools to program the eFPGA matrix and set up the RISC-V application programmable parameters, within a complete and optimized software solution.

About Andes Technology
Andes is a world class creator of innovative high-performance/low-power 32/64-bit processor cores and associated development environment that serves the rapidly growing global market for embedded system applications. As the founding premier member of RISC-V International, Andes is the first mainstream CPU vendor that has adopted the RISC-V as the base of its fifth-generation architecture, the AndeStar™ V5, and delivers highly configurable and performance-efficient CPU cores with full-featured integrated development environment and comprehensive software/hardware. Andes Technology’s comprehensive RISC-V CPU families range from 25-series, advanced 27-series to high-performance superscalar 45-series. For more information, please visit http://www.andestech.com

About Menta
Menta is a privately held company based in Sophia-Antipolis, France. For ASIC and SoCs designers who need fast, right-the-first time design and fast time to volume, Menta is the proven eFPGA pioneer whose design-adaptive standard cells-based architecture and state-of-the-art tool set provides the highest degree of design customization, best-in-class testability and fastest time-to-volume for SoC design targeting any production node at any foundry. For more information, visit the company website at: www.menta-efpga.com.

For more information, contact
Yoan Dupret, Managing Director & VP Business Development
e-mail: yoan.dupret@menta-efpga.com
tel : +33 652 970 251

Imen Baili, Sales Application Engineer
e-mail: imen.baili@menta-efpga.com
tel : +33 783 030 771

Continue ReadingMenta and Andes Announce Partnership Enabling Hardware Reconfiguring for ISA Extension

Imperas Simulator Supports Andes Custom Extension™ to Accelerate Software Development in Domain Specific Applications

HSINCHU, TAIWAN AND OXFORD, UK – December 03, 2020 – Andes Technology Corp., a leading supplier of performance-efficient and extensible 32/64-bit RISC-V CPU cores and a Founding Premier member of the RISC-V International Association, and Imperas Software Ltd., a leader in high-performance software simulation and virtual platforms, announced today to extend their cooperation to the versatile Andes Custom Extension™ (ACE) and Imperas’ fast simulators. The joint work enables SoC design teams using the ACE framework to co-design hardware and software so that full software development can start before the silicon is available.


Under the ACE framework, SoC designers can easily and efficiently define new instructions on the Andes RISC-V processor core to speed up target applications by writing ACE scripts for instruction semantics and concise Verilog for instruction execution RTL. Taking them as inputs, the powerful tool COPILOT (Custom-OPtimized Instruction deveLOpment Tools) automatically generates all required components to extend the existing Andes processor package, including the processor RTL, the compilation tools, the debugger and the near cycle-accurate simulator, to support the new instructions.

While SoC architects and logic designers focus on accelerating the most time critical parts of their applications, software engineers need to ensure the functionality and robustness of the whole software stack and put in new features at the same time. Before the SoC silicon is available for full-speed development, a fast simulator allows software engineers to jump-start the coding, debugging and testing of their applications without depending on the schedule of the hardware development. By taking the extended simulation shared library generated by the COPILOT, the Imperas simulators can automatically recognize the new instructions and simulate their functionality just like a hand-customized simulator. With a fast simulator and the associated tools, software engineers can start full development and even provide feedbacks to hardware designers.

“All Andes RISC-V CPU cores are extensible. ACE empowers SoC designers to easily add custom instructions on top of our highly efficient cores to fulfill domain-specific acceleration and bring their SoC performance to the next level,” says Dr. Charlie Su, Andes Technology CTO and EVP. “Our RISC-V CPU cores are supported by the Imperas simulators already. We are excited to extend our cooperation to enable ACE users to use the Imperas fast simulators so that software engineers can also be engaged with the full development cycle and from the early stage.”

“The flexibility of RISC-V with custom extensions, while compliant with the software ecosystem, offers new degrees of freedom for system architects,” says Simon Davidmann, CEO at Imperas Software Ltd. “Rapid software architectural exploration with virtual platforms complements the ACE hardware implementation flow, plus the resulting platforms offer virtual development boards well before silicon is available. Andes and Imperas working together are helping customers and partners innovate hardware flexibility at the speed of software development.”

The cooperation enhances the ACE solution with the Imperas fast simulators and virtual platforms. SoC design teams using the ACE framework for Andes RISC-V processor cores can define custom instructions and have all the required components generated automatically in no time on their desktops by the COPILOT tool. They include extended components for the processor RTL, the compilation tools, the debugger, the  near cycle-accurate simulator as well as the Imperas fast functional simulators.

About Andes Technology
Fifteen years after starting from scratch, Andes Technology Corporation is now a world class creator of innovative high-performance/low-power 32/64-bit processor cores and associated development environment that serves the rapidly growing global market for embedded system applications. As the founding Premier member of RISC-V International, Andes is the first mainstream CPU vendor that has adopted the RISC-V as the base of its fifth-generation architecture, the AndeStar™ V5. To meet the demanding requirements of today’s electronic devices, Andes delivers highly configurable and performance-efficient CPU cores with full-featured integrated development environment and comprehensive software/hardware solutions to help customers innovate their SoC in a shorter time to market. Since 2018, the yearly volume of SoCs Embedded with Andes CPUs has surpassed the 1-billion mark. Andes Technology’s comprehensive RISC-V CPU families range from the entry-level N22 (32-bit only), mid-range 25-series, advanced 27-series to high-performance superscalar 45-series. For more information, please visit https://www.andestech.com

About Imperas
Imperas is revolutionizing the development of embedded software and systems and is the leading provider of RISC-V processor models and virtual prototype solutions. Imperas, along with Open Virtual Platforms (OVP), promotes open-source model availability for a spectrum of processors, IP vendors, CPU architectures, system IP and reference platform models of processors and systems ranging from simple single core bare metal platforms to full heterogeneous multi-core systems booting SMP Linux. All models are available from Imperas at www.imperas.com and the Open Virtual Platforms (OVP) website at www.ovpworld.org

Continue ReadingImperas Simulator Supports Andes Custom Extension™ to Accelerate Software Development in Domain Specific Applications

Faster, Smaller and More Accurate Edge AI Using Deeplite and Andes Technology Software + Hardware

MONTREAL, CANADA and HSINCHU, TAIWAN – December 1, 2020 – The push for low-power and low-latency deep learning models, computing hardware, and systems for artificial intelligence (AI) inference on edge devices continues to create exciting new opportunities. There has been unprecedented interest from industry stakeholders in the development of hardware and software solutions for on-device deep learning, also called Edge AI. This has already begun to yield progress on hallmark applications such as keyword spotting in audio classification, anomaly detection and, in this case, person detection in computer vision applications. Specifically, tinyML, the branch of machine learning tailored to ultra-low power systems, holds tremendous promise. The efficiency of proposed solutions (milliwatt or even microwatt power consumption) and vast applicability and deployment of such devices in real-world settings will lead to over 100 billion IoT sensors and devices expected to ship over the next 5 years 1. The future of deep learning is poised to provide significant benefits to customers and end-users by way of affordable, eco-friendly and more accessible intelligence than ever before.

Today, Andes Technology and Deeplite Inc. are excited to announce the latest results in their partnership for AI-powered applications using Deeplite’s unique optimization software and Andes’ low-power Andes RISC-V CPU cores. The partnership focuses on compressing and accelerating the well-known Visual Wake Words (VWW) application, where a tiny embedded camera can detect a person in images. Together, Deeplite and Andes achieved industry-leading results, producing various optimized INT8 models from the floating point based Mobilenet-v1-0.25x model. The first set of results focused on increasing accuracy. Our accuracy-focused INT8 model optimization achieves 2.7% higher accuracy, 1.7x (172 KB) smaller size, and 9% faster execution. The second set of results focused on maximizing compression. Our model-size-focused optimization achieved 2.3x (121KB) smaller size, slightly higher accuracy (0.7%), and 15% faster execution when compared to int8 model provided by TensorFlow Lite Micro.

Table 1 Trade-offs in model size, accuracy and execution time for reference and optimized models

“We are determined to provide the most efficient and accurate solutions possible for low-power devices, particularly as edge AI is increasingly deployed in smart assistants, security cameras and smart manufacturing applications.” said Dr. Charlie Su, CTO and Executive VP of Andes Technology. “Deeplite’s cutting-edge software offers an effective way to optimize AI models with enhanced performance to current frameworks. We leverage Deeplite’s abilities for our AndeStar™ V5 architecture, the first commercially available RISC-V CPU cores with DSP SIMD ISA, to enable our customers to use the AI models most suitable for their applications.”

“The Andes™ RISC-V CPU cores provide ideal hardware examples to show the benefits of Deeplite’s model optimization, deploying sophisticated intelligence previously not possible in low cost, battery-powered devices,” said Nick Romano, CEO of Deeplite. “As we continue to produce leading results for the industry’s biggest challenges like Visual Wake Words and keyword spotting, we anticipate a major surge in Edge AI applications powered by Deeplite’s software.”

The combination of industry leading optimization software by Deeplite with Andes’ state of the art RISC-V CPU cores for tinyML can finally unlock Edge AI use cases like voice recognition or person detection to meet microcontroller-level memory and compute requirements. Device OEMs and application developers may now offer users the benefit of keeping their data on-device while still providing the real-time and seamless responses necessary for AI in everyday life.

To access the technical whitepaper and optimization results, contact Anastasia Hamel, Deeplite Marketing Manager at anastasia@deeplite.ai.

1https://review42.com/internet-of-things-stats/ 

About Andes Technology
Fifteen years after starting from scratch, Andes Technology Corporation is now a world class creator of innovative high-performance/low-power 32/64-bit processor cores and associated development environment that serves the rapidly growing global market for embedded system applications. As the founding Premier member of RISC-V International, Andes is the first mainstream CPU vendor that has adopted the RISC-V as the base of its fifth-generation architecture, the AndeStar™ V5. To meet the demanding requirements of today’s electronic devices, Andes delivers highly configurable and performance-efficient CPU cores with full-featured integrated development environment and comprehensive software/hardware solutions to help customers innovate their SoC in a shorter time to market. Since 2018, the yearly volume of SoCs Embedded with Andes CPUs has surpassed the 1-billion mark. Andes Technology’s comprehensive RISC-V CPU families range from the entry-level N22 (32-bit only), mid-range 25-series, advanced 27-series to high-performance superscalar 45-series.

For more information, please visit https://www.andestech.com

About Deeplite
Based in Montreal, Canada, Deeplite is an AI software company dedicated to enabling AI for everyday life. Deeplite uses a proprietary AI software platform to automatically make other AI models faster, smaller and more energy efficient creating highly compact, high-performance deep neural networks for deployment on edge devices such as cameras, sensors, drones, phones and vehicles. Since its inception in 2018, the core technology from Deeplite has enabled some of the world’s most innovative companies to drive more efficient cloud AI inference and unlock new use cases previously not possible for deep learning on embedded and low-power devices.  Deeplite was named to the 2020 CB Insights AI100 list of top 100 privately-held AI companies and has been featured by Gartner, Forbes, and ARM AI as a premier Edge AI innovator. 

For more information, please visit http://www.deeplite.ai

Continue ReadingFaster, Smaller and More Accurate Edge AI Using Deeplite and Andes Technology Software + Hardware

Learn the Latest on RISC-V and Vector Processing at All Six Andes Technology Corporation’s Presentations at the 2020 RISC-V Summit

SAN JOSE, CA – November 05, 2020 – Andes Technology Corporation (TWSE: 6533), a leading supplier of high efficiency, low-power 32/64-bit RISC-V processor cores and founding Premier member of RISC-V International will make six presentations at the virtual RISC-V Summit from December 8 to 10, 2020. 

Andes CTO and Executive VP, Charlie Hong-Men Su, will give an overview and update on “Andes RISC-V Processor IP Solutions.” Andes Senior Director of Architecture Div., Chuan-Hua Chang, will present “AndesClarity: a Performance & Bottleneck Analyzer for RISC-V Vector Processors.” Paul Ku, Deputy Technical Director of Architecture Div., will introduce “Building a Secure Platform with the Enhanced IOPMP.”

The SoC industry has seen fast-growing and diversified demands for a wide range of RISC-V based products: from tiny low-power MCUs for consumer devices, to chips powering enterprise-grade products and datacenter servers; from one power-efficient core to a thousand GHz+ cores working cohesively. Charlie Su will explain the rich portfolio of AndesCore™ RISC-V processor IPs already populating these SoCs: compact single-issue cacheless cores to feature-rich Linux-capable superscalar cores, cache-coherence multicores, and cores capable of processing floating-point and DSP data to those crunching a large volume of vector data. He will also update RISC-V IPs newly added to Andes processor portfolio, the associated software support and their performance data.

Additionally, Deputy Software Manager, Shao-Chung Wang, will present “Extending Multicore Programming Framework for Vector Extension.” Ding-Kai Huang, VLSI Manager, will discuss “Enhancing Verification Coverage for RISC-V Vector Extension Using RISCV-DV,” co-authored with Tao Liu from Google. Andes Principal Architect, Thang Tran, will hold a 3-hour master class entitled “RISC-V Vector Extension Demystified.”

For more information, please visit the RISC-V Summit website.

 

About Andes Technology Corp.
Andes Technology Corporation is a world class creator of innovative high-performance/low-power 32/64-bit processor cores and associated development environment that serves the rapidly growing global market for embedded system applications. As the founding Premier member of RISC-V International, Andes is the first mainstream CPU vendor that adopted the RISC-V as the base of its fifth-generation architecture, the AndeStar™ V5. To meet the demanding requirements of today’s electronic devices, Andes delivers highly configurable and performance-efficient CPU cores. They come with full-featured integrated development environment and comprehensive software/hardware solutions to help designers innovate their SoCs in a shorter time to market. In 2019, the volume of SoCs Embedded with Andes CPUs surpassed the 1.5-billion mark. Andes Technology’s comprehensive RISC-V CPU families range from the entry-level 32-bit N22, mid-range 32-bit N25F/D25F/A25/A27 and 64-bit NX25F/AX25/AX27, to the high-end multicore A(X)25MP and vector processor NX27V. Coming soon is the superscalar 45 series. For more information, please visit http://www.andestech.com/

Continue ReadingLearn the Latest on RISC-V and Vector Processing at All Six Andes Technology Corporation’s Presentations at the 2020 RISC-V Summit

Telink and Andes Announce the TLSR9 SoC with RISC-V Processor

SHANGHAI, CHINA – November 2, 2020 – Telink Semiconductor and Andes Technology are proud to introduce the new connectivity system on a chip (SoC) for Telink’s latest product line, the TLSR9 series. Powered by the Andes RISC-V core D25F, the TLSR9 series is designed for the next generation of hearables, wearables, and other high-performance IoT applications. Thanks to the companies’ partnership with IAR Systems, IoT designers will also have access to the powerful development toolchain IAR Embedded Workbench for flexible product development.

Enabling Innovative New IoT Products

The Telink TLSR9 series is the latest addition to Telink’s line of complete connectivity solutions, and it is designed to maximize device performance and minimize time to market. The TLSR9 series is designed using Andes’ latest AndeStar™ V5 Instruction Set Architecture (ISA), which is compliant to the RISC-V technology. As an open source instruction set architecture (ISA), RISC-V offers developers a great depth of design knowledge and facilitates more innovative and secure processor design.

The TLSR9 SoC features Andes 32-bit RISC-V processor D25F and is the world’s first SoC which adopts RISC-V DSP/SIMD P-extension that is ideal for a variety of mainstream audio, wearables and IoT development needs. The D25F has an efficient 5-stage pipeline and delivers the leading performance of 2.59 DMIPS/MHz and 3.54 CoreMark/MHz at its class. With RISC-V P-extension (RVP), it significantly increases the efficiency for small volume of data computation, and makes the compact AI/ML applications possible on the edge devices. It has been collected that 14.3x speedup of CIFAR-10 AI models, which is a typical image classification technology, and 8.9x speedup of keyword spotting technology, which consumed only dozens of million cycles per inference. Furthermore, the standard JTAG and Andes 2-wire serial debugging port helps to reduce the pin cost.

“We are excited to announce the news,” said Dr. Wenjun Sheng, CEO of Telink Semiconductor.“Telink has always been dedicated to building the future of the Internet of Things and consumer electronics. That means continuously exploring new ways to make chips that are at once more powerful and easier to put into action. By partnering with Andes Technology and IAR Systems to provide a top-notch processor and IDE for our new TLSR9 product line, we are committed to reducing the difficulty of application development and improving efficiency. Telink will continue to provide quick-to-market, performance enhanced, cost efficient solutions to our customers.”

“We believe the RVP is going to open a new era for data computation on MCU.” said Frankwell Lin, President of Andes Technology.“We are gratefully to cooperate with Telink and IAR to build the foundation of the RVP ecosystem for edge AIoT. With Telink TLSR9 and IAR EWRISC-V, developers can easily bring into full play the advantage of RVP. Andes contributed the first version of RVP specification to RISC-V last year, and it is at version 0.8 now. We are looking forward to ratification of RVP standard to enable more and more AIoT market for RISC-V with our partners.”

“We are happy to partner with Andes and Telink to deliver innovative new solutions for IoT developers,” says Kiyofumi Uemura, APAC Director, IAR Systems. “Together we have a lot to offer with regards to performance, and by providing maximized code speed and minimized code size for the TLSR9 series, we will create new possibilities to reduce time to market and ensure high quality applications.”

About Telink Semiconductor
Founded in 2010, Telink Semiconductor is a fabless integrated circuit design company with offices in Shanghai, Shenzhen, Taipei, Santa Clara, and London. Telink is dedicated to the development of highly integrated low-power radio frequency and mixed signal system chips for Internet of Things applications. Telink’s product portfolio is aimed at serving markets ranging from smart lighting to home automation to smart cities and currently includes 2.4GHz RF SoCs for Bluetooth, Zigbee, 6LoWPAN/Thread, and HomeKit. Visit Telink at http://www.telink-semi.com.

About Andes Technology
Fifteen years in business and a founding Premier member of RISC-V International, Andes Technology is a leading supplier of high-performance, low-power 32/64-bit embedded processor IP solutions and a major player in pushing RISC-V into the mainstream. Andes’ fifth-generation AndeStar™ architecture adopted the RISC-V as its base. Its V5 RISC-V CPU families range from tiny 32-bit cores to advanced 64-bit cores with DSP, FPU, Vector, Linux, dual-issue, and/or multi-core capabilities. Visit Andes at https://www.andestech.com

Continue ReadingTelink and Andes Announce the TLSR9 SoC with RISC-V Processor