A Look Back at the Achievements Andes Made in 2019

As the world class creator of innovative high-performance/low-power 32/64-bit processor cores, Andes Technology has devoted itself to promoting RISC-V and bringing fruitful results. In 2019, it has launched more diverse and powerful RISC-V processors and also turned to be Founding Platinum Member in the RISC-V Foundation. In the coming year, Andes will continue driving innovation and taking RISC-V to the mainstream market!

  • Andes upgraded its membership in the RISC-V Foundation to Platinum.


  • Andes President Frankwell Lin becomes Vice President of RISC-V Taiwan Alliance, founded in 2019.

  • Over 200 commercial licensees, geographically distributed in Taiwan, China, Korea, Japan, Europe, and USA.

  • Over 350 license agreements signed.

  • Over 17,000 installations of AndeSight™ IDE.

  • Over 145 ecosystem partners.

  • The cumulative shipment of SoCs embedded with Andes CPU cores surpassed 4.5 billion.

  • This year, through the end of the third quarter, the top three rankings of revenue by regions are Taiwan(38%), USA(31%) and China (25%).

  • This year, through the end of the third quarter, the ratio of total revenue by products are RISC-V(49%), V3(34%) and Customer Computing(17%).

  • This year, through the end of the third quarter, top three customer applications are AI (22%), Sensing (22%) and IoT (15%) based on agreement number.


  • Andes has launched AndesCore™ RISC-V multi-core processors A25MP/AX25MP and announced that AndesCore™ 27-series processor, AndesCore™ 45-series processors and RISC-V vector extension processor will be available in 2020.

  • Andes targeted deeply embedded protocol processing and entry-level MCUs with the new N22, the smallest RISC-V core in its V5 family and launched RISC-V FreeStart Program with N22.


  • As a major contributor and maintainer of RISC-V open source software as well as the chair of the P-extension (Packed SIMD/DSP) Task Group and co-chair of Fast Interrupt Task Group, Andes has donated RISC-V P-extension draft to the RISC-V Foundation.

  • Andes Corvette-F1 N25 platform became one of the first RISC-V platforms qualified for Amazon FreeRTOS.

  • Andes strengthened the RISC-V EasyStart alliance to more than 15 ASIC design service partners.
  • Andes and Silex Insight built strategic partnership for RISC-V based root-of-trust IP solutions.

  • Secure-IC and Andes teamed up to provide cybersecurity enhanced RISC-V cores.

  • SEGGER makes its entire ecosystem of tools available for AndesCores.

  • Andes and Deeplite joined forces to deploy highly compact deep learning models into daily life.

  • Andes and Tiempo Secure announced strategic partnership to enhance RISC-V platform security up to CC EAL5+ certification.

  • Andes and Dover Microsystems partnered to deliver professional network security solution for RISC-V.

  • Andes hosted five RISC-V CON in total in Hsinchu, Shanghai, Shenzhen, Beijing and Silicon Valley. More than 1,000 RISC-V enthusiasts around the world joined us to learn the market trends and our leading technology.


  • Andes also participates in the RISC-V Foundation Marketing Committee and APAC Promotion Task Group to help drive RISC-V’s global expansion. Andes joined every RISC-V workshop in Asia, EU, and the US, and one-day RISC-V roadshows in 15 cities around the world.


  • Andes joined almost 60 major industry events around the world, including Embedded World (Germany), RISC-V Panel (Hsinchu), RISC-V Workshop (Hsinchu, Zurich), RISC-V Roadshow (US*4, EMEA*6, China*5), TSMC Technology Symposium (Santa Clara, Boston, Austin, Hsinchu, Amsterdam, Shanghai, Israel, Japan), TSMC OIP Ecosystem Forum (Amsterdam, Santa Clara, Beijing), IP SoC Day (Santa Clara, Shanghai, Grenoble), Linley Spring Processor Conference (Santa Clara), RISC-V Meetup (Santa Clara), COMPUTEX (Taipei), DAC (San Francisco), RISC-V Seminar (Korea), TechTaipei (Taipei), VLSI Design/CAD Symposium (Kaoshiung), IC Innovative Application Summit (Shenzhen), IC China (Shanghai), MIITEC conference , SMIC Symposium (Shanghai), RISC-V Day (Tokyo), SEDEX (Korea), WIOTC (Wuzhen), KUMICO Meetup (Tokyo, Osaka), IAR DevCon (Tokyo), China RISC-V Forum (Shenzhen), China High-Tech Fair (Shenzhen), Semisrael Expo (Israel), ET & IoT Technology (Yokohama), ICCAD (Nanjing), RISC-V Summit (Santa Clara), ELEXCON (Shenzhen)。

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Andes Corvette-F1 N25 Platform Becomes one of the first RISC-V Platforms Qualified for Amazon FreeRTOS

San Jose, California, December 9th, 2019 – Andes Technology, a leading supplier of high-performance low-power compact 32/64-bit RISC-V CPU cores and a founding member of the RISC-V Foundation, today announced its Corvette-F1 N25 platform is one of the first RISC-V platforms qualified for Amazon FreeRTOS. Amazon FreeRTOS is an open source operating system for microcontrollers from Amazon Web Services (AWS) that makes small, low-power edge devices easy to program, deploy, secure, connect, and manage. Developers can take advantage of Amazon FreeRTOS features and benefits by using the RISC-V platform from Andes Technology.

“IoT, and AIoT, will be a big addressable market for RISC-V CPU,” said Dr. Charlie Su, CTO and Executive VP of Andes Technology. “By leveraging the advantages of Amazon FreeRTOS and Andes RISC-V platform, we can provide developers using Amazon FreeRTOS additional development platform choices and strengthen the Andes RISC-V IoT solutions for our customers.”

As more and more technologies have been deployed to the internet, the IoT market grows with a wide variety of diversified applications. The RISC-V Instruction Set Architecture (ISA) provides enhanced flexibility, extensibility, and scalability that can help generate new possibilities for the IoT and making it easier to design compact IoT hardware to take advantage of this growing market. By combining the RISC-V platform with solutions like Amazon FreeRTOS, AWS IoT Greengrass, and AWS IoT Core, Andes Technology can help developers to create comprehensive and competitive RISC-V-based IoT systems.


The Corvette-F1 N25 platform is a FPGA-based Arduino-compatible evaluation platform. It comes with a 32-bit RISC-V AndesCore™ N25 running at 60MHz, 4MB Flash, 256KB instruction SRAM and 128KB data SRAM, and AndeShape™ AE250 Platform IP with rich peripherals such as GPIO, I2C, PWM, SPI, and UART. It also contains an on-board wireless module supporting IEEE 802.11 b/g/n. For more information about Andes Corvette-F1 N25 platform, please visit http://www.andestech.com/en/products-solutions/andeshape-platforms/corvette-f1-n25/

Continue ReadingAndes Corvette-F1 N25 Platform Becomes one of the first RISC-V Platforms Qualified for Amazon FreeRTOS

Andes Technology Announces Coming Up the North America Annual RISC-V CON 2019 Santa Clara

Santa Clara, US – September 24, 2019 – The RISC-V CON 2019 held in Santa Clara on October 15 will feature the first independent analysis of the commercial potential for the open source architecture RISC-V market opportunity. Jim Feldhan, President of Semico Research will present the findings of his firm’s evaluation based on research commissioned by the RISC-V Foundation. Amazon will provide a RISC-V user’s perspective in a technical presentation detailing an AI compiler based on RISC-V. Imperas will release their next generation software tools for developing RISC-V based SoCs. Faraday will offer a design service’s viewpoint on building a RISC-V based ASIC solution for edge AI and IoT SoC.

Andes Technology CTO and Executive VP Charlie Su, will present “Powering RISC-V SoCs with 1 to 1,000s AndesCores.” His presentation will illustrate the range and versatility of the RISC V instruction set architecture (ISA) that is propelling the ISA’s widespread adoption by everyone from start-ups to Fortune 500 companies in applications spanning Internet of Things to multiprocessor AI devices. To conclude up the seminar, a panel moderated by Jim Feldhan will discuss how Andes, Amazon, Imperas and Faraday are driving RISC-V adoption.

During RISC-V CON, presentations, partner exhibitions and live demo will enable attendees to learn more about the advanced RISC-V ISA technology. Through face-to-face interactions with RISC-V ecosystems and partners, attendees will get more latest, leading-edge information on this rapidly emerging new CPU architecture. For more information about RISC-V CON, please visit http://www.andestech.com/Andes_RISC-V_CON_2019_US/

About RISC-V CON
In order to foster stronger collaboration on RISC-V across the computing industry, RISC-V CON focuses on this disruptive technology, demonstrating its benefits and identifying commercial strategies. Through RISC-V CON, the RISC-V community and ecosystem can share the most up-to-date development and RISC-V based products and solutions.

With more than 14 years focusing on the CPU IPs, Andes Technology, the most experienced vendor of RISC-V processors and solutions, has launched many new RISC-V based products. By bringing together industry experts, the goal is to make it easier for other industry players to quickly bring innovative designs based on the open RISC-V ISA to market.

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Andes Technology Features 32-bit A25MP and 64-bit AX25MP RISC-V Multicore Processors With Andes Custom Extension at TSMC 2019 Open Innovation Platform® Ecosystem Forum

A25MP and AX25MP are Cache Coherent RISC-V Multicore Processors
With Comprehensive DSP Instruction Extension and Custom Extensions for AI and ADAS Designs

HSINCHU, TAIWAN – September 24, 2019 – Andes Technology Corporation, a leading supplier of small, low-power, high performance 32/64-bit embedded CPU cores, including a broad family of RISC-V cores, announced that it will be participating in the TSMC 2019 Open Innovation Platform® Ecosystem Forum, on September 26, 2019 at the Santa Clara Convention Center. Andes Technology will feature its latest generation 32-bit A25MP and 64-bit AX25MP RISC-V Multicore Processors with Andes Custom Extensions, that allows designers to create special instructions to accelerate compute intensive functions, a capability highly desired in AI and ADAS designs. The cache coherent A25MP and AX25MP RISC-V multicore processors are the company’s first with comprehensive DSP instruction extension based on the RISC-V P-extension draft Andes donated to the RISC-V Foundation.

“The A25MP and AX25MP have already achieved major design wins in high-performance artificial intelligence applications and the product family has seen strong interest from Fortune 500 companies,” said Andes Technology Corp. President, Frankwell Lin. “Multiple processor cores extended with Andes Custom Extensions working in parallel enable computation intensive applications, such as artificial intelligence and Advanced Driver-Assistance Systems (ADAS) to significantly boost their performance. Furthermore, the DSP/SIMD ISA, executing the CIFAR-10 dataset (Canadian Institute For Advanced Research) image classification benchmark for machine learning achieved an order of magnitude performance boost. It also achieved 7 times acceleration in the PNET for MtCNN (Multi-task Cascaded Convolutional Networks) face detection and alignment algorithm.”

“The A25MP and AX25MP support up to four CPU cores,” said Dr. Charlie Su, CTO and EVP of Andes Technology Corp. “The processors’ hardware-managed cache coherence simplifies software design considerably for systems with multiple CPUs. They provide efficient cache coherence among private level-1 caches, include an optional shared level-2 cache and support I/O coherence for bus masters without caches. Besides that, using Andes Custom Extension™ (ACE) designers can increase performance by adding their own CPU instructions specifically for the target applications on the already optimized AndesCore™ processors and eliminate the software bottlenecks. Operating at over 1GHz in a 28nm process with Linux symmetric multiprocessing (SMP) support, the A25MP and AX25MP raise the RISC-V processors to the next performance level and widens its market potential.”

For more information about the A25MP/AX25MP multicores, please visit Andes Technology Corp. in booth 308 at TSMC 2019 Open Innovation Platform® Ecosystem Forum exhibition on September 26, 2019 at the Santa Clara Convention Center. In addition, please see Andes Technology Corp.’s presentation “Implementing Customized RISC-V CPUs in Machine Learning Applications,” in TSMC 2019 Open Innovation Platform® Ecosystem Forum printed proceedings. You can also learn about the A25MP and AX25MP cores as well as all Andes CPU core on our website http://www.andestech.com/en/products-solutions/andescore-processors/

Continue ReadingAndes Technology Features 32-bit A25MP and 64-bit AX25MP RISC-V Multicore Processors With Andes Custom Extension at TSMC 2019 Open Innovation Platform® Ecosystem Forum

SEGGER Makes Its Entire Ecosystem of Tools Available for AndesCores

MONHEIM, GERMANY – September 18, 2019 – SEGGER, leading supplier of software libraries, development tools, debug probes and flash programmers, together with Andes, a founding member of the RISC-V Foundation and the leading supplier of 32/64-bit embedded CPU cores, today announce their collaboration to support the complete development process of embedded systems based on Andes RISC-V CPUs with easy to use, efficient and reliable, tools and libraries.

The entire palette of SEGGER software libraries, from the RTOS embOS to file system, compression, graphics library, security, communication and IoT, as well as SEGGER’s integrated development environment Embedded Studio, already support all of Andes RISC-V processors. SEGGER’s J-Link debug probes and Flasher flash programmers currently support Andes RISC-V 32-bit CPU cores, including N25F, D25F and A25, with support for 64-bit CPU cores in the works.

Andes Technology Corporation is a leading embedded processor intellectual property supplier. Since 2005, the company has developed high-performance, low-power processors and their associated SoC platforms to serve the rapidly growing global embedded system applications. Up to the end of 2018, the cumulative volume of Andes-Embedded™ SoCs has reached 3.5 billion with 2018 alone contributing over 1 billion.

“We are excited to cooperate with Andes,” says Ivo Geilenbrügge, Managing director of SEGGER. “Our software tools and libraries, especially J-Link and Embedded Studio, significantly enhance the Andes RISC-V ecosystem. We offer a comprehensive one-stop solution for firmware and application developers.”

“We are excited to partner with SEGGER and have their entire product palette available to our RISC-V cores,” comments Dr. Charlie Su, CTO and Executive VP, Andes Technology Corporation. “SEGGER provides a complete ecosystem for all embedded needs. With J-Link and Embedded Studio, Andes now has the leading development solution. Fast and powerful: It simply works. Together, we offer powerful solutions for Andes V5 RISC-V extended ISA to serve diversified SoCs from our customers.”

For more information about SEGGER development solutions, click https://www.segger.com/

For more information about Andes RISC-V processors, click http://www.andestech.com/en/risc-v-andes/

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