Andes and Dover Microsystems Partner to Deliver Professional Network Security Solution for RISC-V

HSINCHU, TAIWAN , Sept. 25, 2019 – Andes Technology Corporation (TWSE: 6533), a founding member of the RISC-V Foundation and the leading supplier of 32/64-bit embedded CPU cores with solutions serving in excess of 1-billion diversified SoCs yearly, and Dover Microsystems, the first company to immunize processors against entire classes of network-based attacks, announced a strategic partnership to deliver professional network security solution for RISC-V. Dover’s CoreGuard® technology is the only solution for embedded systems that prevents the exploitation of software vulnerabilities. Dover’s CoreGuard silicon IP integrates with Andes RISC-V processors to protect against 94% of known software vulnerabilities, including 100% buffer overflows, code injection, and data exfiltration as well as safety violations.

Andes RISC-V processors are based on AndeStar™ V5 architecture, which maintains the full compatibility to RISC-V technology and thus inherits its compact, modular and extensible advantages. In addition, AndeStar V5 architecture brings Andes-extended features already proven in high-volume V3 AndesCore™ processors to be effective and beneficial to embedded applications with enhanced performance, code size and development support. Andes RISC-V cores include ultra-compact 32-bit N22 for applications such as entry-level microcontrollers and deeply-embedded protocol processing, 32-bit D25F for signal processing applications, 32/64-bit N25F/NX25F for high-speed control tasks or floating-point intensive applications, A25/AX25 for Linux-based applications and A25MP/AX25MP for cache coherence multi-core applications.

Dover Microsystems’ CoreGuard silicon IP acts as a bodyguard to the host processor, monitoring every instruction executed to ensure that it complies with a defined set of security, safety, and privacy rules – called micropolicies – that precisely define allowed versus disallowed behavior. CoreGuard maintains micropolicy-relevant metadata about every word in memory, and then uses this metadata to crosscheck each instruction processed against the installed set of micropolicies. If an instruction violates any micropolicy, CoreGuard Policy Enforcer hardware stops it from executing before any damage is done. CoreGuard Policy Enforcer RTL is licensed and delivered as a set of hardware SystemVerilog design files. Dover includes the base set of CoreGuard micropolicies that protect all embedded systems.

“Andes is determined to provide the best RISC-V solutions to help our customers design SoC exceeding their expectations. We understand that network security is a major concern of many IoT applications,” said Dr. Charlie Su, CTO and Executive VP of Andes Technology. “With the pre-integrated, verified solution of industry-leading CoreGuard technology from Dover Microsystems and the leading performance-efficient RISC-V processors with rich features for embedded systems from Andes Technology, SoC designers gain quick access to a mature RISC-V solution with outstanding performance and network security.”

“Our CoreGuard silicon IP integrates with existing RISC processors to protect embedded systems against security, safety, and privacy threats,” said Jothy Rosenberg, Founder and CEO of Dover Microsystems. “The integration of CoreGuard with the high-quality AndesCore RISC-V processor is clean and straightforward, providing customers with the most powerful and easy to adopt security solution that immunizes SoCs against network-based cyberattacks.”

For more information about Andes RISC-V processors, click http://www.andestech.com/markets.php.
For more information about Dover Microsystems CoreGuard®, click https://www.dovermicrosystems.com/solutions/coreguard

Continue ReadingAndes and Dover Microsystems Partner to Deliver Professional Network Security Solution for RISC-V

Andes Technology Announces Coming Up the North America Annual RISC-V CON 2019 Santa Clara

Santa Clara, US – September 24, 2019 – The RISC-V CON 2019 held in Santa Clara on October 15 will feature the first independent analysis of the commercial potential for the open source architecture RISC-V market opportunity. Jim Feldhan, President of Semico Research will present the findings of his firm’s evaluation based on research commissioned by the RISC-V Foundation. Amazon will provide a RISC-V user’s perspective in a technical presentation detailing an AI compiler based on RISC-V. Imperas will release their next generation software tools for developing RISC-V based SoCs. Faraday will offer a design service’s viewpoint on building a RISC-V based ASIC solution for edge AI and IoT SoC.

Andes Technology CTO and Executive VP Charlie Su, will present “Powering RISC-V SoCs with 1 to 1,000s AndesCores.” His presentation will illustrate the range and versatility of the RISC V instruction set architecture (ISA) that is propelling the ISA’s widespread adoption by everyone from start-ups to Fortune 500 companies in applications spanning Internet of Things to multiprocessor AI devices. To conclude up the seminar, a panel moderated by Jim Feldhan will discuss how Andes, Amazon, Imperas and Faraday are driving RISC-V adoption.

During RISC-V CON, presentations, partner exhibitions and live demo will enable attendees to learn more about the advanced RISC-V ISA technology. Through face-to-face interactions with RISC-V ecosystems and partners, attendees will get more latest, leading-edge information on this rapidly emerging new CPU architecture. For more information about RISC-V CON, please visit http://www.andestech.com/Andes_RISC-V_CON_2019_US/

About RISC-V CON
In order to foster stronger collaboration on RISC-V across the computing industry, RISC-V CON focuses on this disruptive technology, demonstrating its benefits and identifying commercial strategies. Through RISC-V CON, the RISC-V community and ecosystem can share the most up-to-date development and RISC-V based products and solutions.

With more than 14 years focusing on the CPU IPs, Andes Technology, the most experienced vendor of RISC-V processors and solutions, has launched many new RISC-V based products. By bringing together industry experts, the goal is to make it easier for other industry players to quickly bring innovative designs based on the open RISC-V ISA to market.

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Continue ReadingAndes Technology Announces Coming Up the North America Annual RISC-V CON 2019 Santa Clara

Andes Technology Features 32-bit A25MP and 64-bit AX25MP RISC-V Multicore Processors With Andes Custom Extension at TSMC 2019 Open Innovation Platform® Ecosystem Forum

A25MP and AX25MP are Cache Coherent RISC-V Multicore Processors
With Comprehensive DSP Instruction Extension and Custom Extensions for AI and ADAS Designs

HSINCHU, TAIWAN – September 24, 2019 – Andes Technology Corporation, a leading supplier of small, low-power, high performance 32/64-bit embedded CPU cores, including a broad family of RISC-V cores, announced that it will be participating in the TSMC 2019 Open Innovation Platform® Ecosystem Forum, on September 26, 2019 at the Santa Clara Convention Center. Andes Technology will feature its latest generation 32-bit A25MP and 64-bit AX25MP RISC-V Multicore Processors with Andes Custom Extensions, that allows designers to create special instructions to accelerate compute intensive functions, a capability highly desired in AI and ADAS designs. The cache coherent A25MP and AX25MP RISC-V multicore processors are the company’s first with comprehensive DSP instruction extension based on the RISC-V P-extension draft Andes donated to the RISC-V Foundation.

“The A25MP and AX25MP have already achieved major design wins in high-performance artificial intelligence applications and the product family has seen strong interest from Fortune 500 companies,” said Andes Technology Corp. President, Frankwell Lin. “Multiple processor cores extended with Andes Custom Extensions working in parallel enable computation intensive applications, such as artificial intelligence and Advanced Driver-Assistance Systems (ADAS) to significantly boost their performance. Furthermore, the DSP/SIMD ISA, executing the CIFAR-10 dataset (Canadian Institute For Advanced Research) image classification benchmark for machine learning achieved an order of magnitude performance boost. It also achieved 7 times acceleration in the PNET for MtCNN (Multi-task Cascaded Convolutional Networks) face detection and alignment algorithm.”

“The A25MP and AX25MP support up to four CPU cores,” said Dr. Charlie Su, CTO and EVP of Andes Technology Corp. “The processors’ hardware-managed cache coherence simplifies software design considerably for systems with multiple CPUs. They provide efficient cache coherence among private level-1 caches, include an optional shared level-2 cache and support I/O coherence for bus masters without caches. Besides that, using Andes Custom Extension™ (ACE) designers can increase performance by adding their own CPU instructions specifically for the target applications on the already optimized AndesCore™ processors and eliminate the software bottlenecks. Operating at over 1GHz in a 28nm process with Linux symmetric multiprocessing (SMP) support, the A25MP and AX25MP raise the RISC-V processors to the next performance level and widens its market potential.”

For more information about the A25MP/AX25MP multicores, please visit Andes Technology Corp. in booth 308 at TSMC 2019 Open Innovation Platform® Ecosystem Forum exhibition on September 26, 2019 at the Santa Clara Convention Center. In addition, please see Andes Technology Corp.’s presentation “Implementing Customized RISC-V CPUs in Machine Learning Applications,” in TSMC 2019 Open Innovation Platform® Ecosystem Forum printed proceedings. You can also learn about the A25MP and AX25MP cores as well as all Andes CPU core on our website http://www.andestech.com/en/products-solutions/andescore-processors/

Continue ReadingAndes Technology Features 32-bit A25MP and 64-bit AX25MP RISC-V Multicore Processors With Andes Custom Extension at TSMC 2019 Open Innovation Platform® Ecosystem Forum

SEGGER Makes Its Entire Ecosystem of Tools Available for AndesCores

MONHEIM, GERMANY – September 18, 2019 – SEGGER, leading supplier of software libraries, development tools, debug probes and flash programmers, together with Andes, a founding member of the RISC-V Foundation and the leading supplier of 32/64-bit embedded CPU cores, today announce their collaboration to support the complete development process of embedded systems based on Andes RISC-V CPUs with easy to use, efficient and reliable, tools and libraries.

The entire palette of SEGGER software libraries, from the RTOS embOS to file system, compression, graphics library, security, communication and IoT, as well as SEGGER’s integrated development environment Embedded Studio, already support all of Andes RISC-V processors. SEGGER’s J-Link debug probes and Flasher flash programmers currently support Andes RISC-V 32-bit CPU cores, including N25F, D25F and A25, with support for 64-bit CPU cores in the works.

Andes Technology Corporation is a leading embedded processor intellectual property supplier. Since 2005, the company has developed high-performance, low-power processors and their associated SoC platforms to serve the rapidly growing global embedded system applications. Up to the end of 2018, the cumulative volume of Andes-Embedded™ SoCs has reached 3.5 billion with 2018 alone contributing over 1 billion.

“We are excited to cooperate with Andes,” says Ivo Geilenbrügge, Managing director of SEGGER. “Our software tools and libraries, especially J-Link and Embedded Studio, significantly enhance the Andes RISC-V ecosystem. We offer a comprehensive one-stop solution for firmware and application developers.”

“We are excited to partner with SEGGER and have their entire product palette available to our RISC-V cores,” comments Dr. Charlie Su, CTO and Executive VP, Andes Technology Corporation. “SEGGER provides a complete ecosystem for all embedded needs. With J-Link and Embedded Studio, Andes now has the leading development solution. Fast and powerful: It simply works. Together, we offer powerful solutions for Andes V5 RISC-V extended ISA to serve diversified SoCs from our customers.”

For more information about SEGGER development solutions, click https://www.segger.com/

For more information about Andes RISC-V processors, click http://www.andestech.com/en/risc-v-andes/

Continue ReadingSEGGER Makes Its Entire Ecosystem of Tools Available for AndesCores

Andes Records Rapid Growth of RISC-V Processors Licensing Agreements in the First Half of 2019

Andes Signed over 60 RISC-V IP License Contracts in the First Half of 2019 Serving Multiple Applications throughout Many Countries Worldwide

HSINCHU, TAIWAN – August 6, 2019 – Andes Technology Corporation, a leading supplier of outstanding efficiency, low-power, high performance 32/64-bit embedded CPU cores, including a broad family of RISC-V cores, announced it achieved a record of 60 licensing agreements for its new family of RISC-V processors during the first half of 2019. After working in the CPU IP field for many years, Andes Technology joined the RISC-V Foundation as a founding member in 2016, while keeping innovating new high-quality RISC-V products. Now the design wins are going into a wide range of applications, including artificial intelligence designs, where RISC-V plays an important role. Other applications adopting RISC-V include ADAS, blockchain, communications, IoT security platform, FPGA, IoT, data center server applications, and solid-state storage devices.

In 2019, Andes launched more series of new RISC-V cores. It includes the innovative 32-bit A25MP and 64-bit AX25MP, multi-core processors supporting up to four CPU cores that provide efficient cache coherence among private level-1 caches. The A25MP and AX25MP also support Linux with complete DSP instruction set. In addition, Andes’ new 32-bit D25F is a low-power, high-performance core with DSP instruction set that serves DSP applications without Linux. Andes’ 32-bit A25 and 64-bit AX25 which support Linux and floating-point operations have also been upgraded to support the DSP instruction set. Andes’ popular 32-bit N22 provides flexible configurability and high efficiency. With its short 2-stage pipeline it achieves impressive performance of 3.95 CoreMark/MHz that makes it suitable in entry-level MCU applications such as small IoT and wearable devices. With years of experience in developing and supplying CPU IP, Andes Technology has accurately grasped the real needs of customers for RISC-V core processors and has achieved the greatest competitive advantage.

Because of features such as open-source ISA, compact, modular and extensible, RISC-V’s market potential has aroused widespread attention and future development. In China, with government support, many RISC-V enthusiasts are actively involved in developing a wide range of RISC-V applications. This RISC-V boom has accelerated industry acceptance and has generated a flourishing hardware and software RISC-V ecosystem. Andes’ customers have achieved significant technology advancements, such as integrating large numbers of CPU cores on a single chip for efficient multiplexed calculations in applications such as AI.

In the first half of 2019, Andes launched the RISC-V FreeStart program offering its commercial-grade CPU N22 RISC-V core with no upfront license fee. The fast and easy FreeStart authorization process has achieved record responses from the industry and academic institutions, and it will help proliferate the number and variety of RISC-V applications.

“The growth of the RISC-V market is only in its infancy,” stated Andes Technology President Frankwell Jyh-Ming Lin. “Our customers’ applications are very diverse and include AI, IoT, ADAS, Netcom and consumer electronics. Customers choose Andes RISC-V solutions because of the technical support of its RISC-V products line, friendly interface and excellent products and solutions. Andes will continue to invest in developing RISC-V related products and environment, and work together with customers and partners to win new business opportunities.”

“Andes supports the technical and marketing committees of the RISC-V Foundation,” declared Andes CTO and Executive Vice President, Charlie Hong-Men Su. “In addition to contributing to the core technology and cooperating with the world’s major companies to develop the RISC-V architecture, Andes leads the latest trends in RISC-V technology. Andes’ advantage is that designers can customize the RISC-V IP product to optimize the CPU IP and expand the function for further enhancement of the overall performance. Custom instruction extensions are easily added using Andes Custom Extension™ (ACE). In addition, Andes’s RISC-V customers can also avail themselves of Andes technology including StackSafe™ for hardware stack protection, CoDense™ for code size compression, PowerBrake for power management and the professional software development environment AndeSight™ IDE for acceleration SoC development.”

About Andes RISC-V Contributions
In addition to expanding its product line and application areas, Andes also actively participates in the RISC-V communities and promotes its diverse marketing activities. Andes has taken part in more than 30 industry events that promoting RISC-V technology around the world in the first half of 2019. RISC-V CON in Shanghai, Shenzhen, Beijing and Hsinchu is an annual series of RISC-V workshops. The attendees engaged with one another and conduct in-depth discussions with speakers. Andes also participated in other activities including the RISC-V Foundation RISC-V Workshop organized in Hsinchu and Zurich and the RISC-V one-day seminar in nine cities in the US and China. Andes joined TSMC OIP (Open Innovation Platform) Forum in Europe to speak about RISC-V applications implemented in TSMC processes. These activities promote potential customers’ understanding of the RISC-V architecture and accelerate the expansion of the RISC-V ecosystem. RISC-V CON’s series of activities will be held in Silicon Valley on October 15 and in Beijing on November 14 during the second half of 2019. The speaker partners include major RISC-V technology industry contributors, such as the expert from Amazon. RISC-V CON continues to bring the latest RISC-V trends to its expanding audience.

Continue ReadingAndes Records Rapid Growth of RISC-V Processors Licensing Agreements in the First Half of 2019

Andes Technology and Silex Insight Announce Strategic Partnership for RISC-V Based Root-of-Trust IP Solutions

July 1, 2019

Andes Technology, Hsinchu, Taiwan

Silex Insight, Mont-Saint-Guibert, Belgium

Andes Technology, a leading Asia-based supplier of high-performance low-power compact 32/64-bit RISC-V CPU cores, and Silex Insight, a leading provider for flexible security IP cores, are announcing a strategic partnership to bring flexible and energy efficient Root-of-Trust security IP solution based on RISC-V to the industry.

Silex Insight’s advanced eSecure IP module is a complete solution that enables security applications by shielding confidential information from non-secure applications running on main processor along with security boot, sensitive key materials and assets protection. AndesCore™ N22, a high-efficiency and low-power 2-stage pipeline RISC-V CPU core, is tightly integrated in the eSecure IP module to fully and robustly control the execution of security functions. eSecure module is highly configurable and thus provides a wide-range selection of security features, performance, area and energy consumption that is suitable for many applications such as IoT, storage, and communication.

“We are able to deliver a ready-to-go solution to SoC makers who need advanced security and efficiency”, says Pieter Willems, Director Sales and Marketing Security Products at Silex Insight and he continues; “With Andes’ N22 RISC-V CPU core integrated in our eSecure Root-of-Trust turnkey solution, customers who demand high security on their devices can easily prevent hostile attacks from the outside world.”

“Root-of-Trust is now fundamental to many devices and connected services,” answers Dr. Charlie Su, CTO and Executive VP of Andes Technology. “We are excited to be able to deliver configurable and efficient security turnkey solution to SoC design companies, thanks to our ultra-compact RISC-V compliant processor N22, included in Silex Insight eSecure IP module platform.”

This robust secure solution is perfect for security-sensitive applications and it is available now from both Andes Technology and Silex Insight.

About Andes Technology

Andes Technology Corporation is a world class creator of innovative high-performance/low-power 32/64-bit processor cores and associated development environment to serve the rapidly growing global embedded system applications. The company delivers superior low power CPU cores, including the comprehensive RISC-V V5 family of processor cores, with integrated development environment and associated software/hardware solutions for efficient SoC design. Up to the end of 2018, the cumulative volume of Andes-Embedded™ SoCs has reached 3.5 billion with 2018 alone contributing over 1 billion. Andes Technology’s comprehensive CPU line includes entry-level, mid-range, high-end, extensible and security families. For more information, please visit www.andestech.com

About Silex Insight

Founded in 1991, Silex Insight is a recognized market-leading independent supplier Security IP solutions for embedded systems. The security platforms and solutions from Silex Insight include flexible  and high-performance crypto-engines which are easy to integrate and a eSecure IP module which provides a complete security solution for all platforms. Development and manufacturing take place at the headquarters near Brussels, Belgium. Local sales and support are handled by worldwide branch offices. For more information visit: www.silexinsight.com

PRESS CONTACT:

Andes Technology Corporation:               
Hsiao-Ling Lin
Marketing Manager
E: hllin@andestech.com
M:+886 3 5726533
Web: www.andestech.com

Silex Insight:
Jon Jacobsen
Marketing Manager
E: marketing@silexinsight.com
M: +32 475 50 30 37
Web: www.silexinsight.com

Continue ReadingAndes Technology and Silex Insight Announce Strategic Partnership for RISC-V Based Root-of-Trust IP Solutions

Andes Technology Launches RISC-V FreeStart Program with its Commercial-Grade CPU N22

AndesCore™ RISC-V CPU IP N22 integrated with interrupt controller, local memory, instruction cache, debug support, and an optional AHB platform

 

HSINCHU, TAIWAN – June 10, 2019 – Andes Technology Corporation, a leading supplier of high performance, low-power, compact 32/64-bit CPU cores embedded in over 1 billion SoC in 2018 alone, today announces its RISC-V FreeStart program. The program offers an easy and fast way to build a solid SoC foundation on the commercial-grade RISC-V CPU core N22, available for free download. AndesCore™ N22 is an entry-level, ultra-compact, low-power and performance-efficient RISC-V CPU IP. It delivers the highest 3.95 Coremark/MHz in its class, and offers rich configurable features, including multiplier, interrupt controller, local memory, instruction cache, debug support, and an optional AHB platform. With the RISC-V FreeStart program, SoC engineers can begin designing a RISC-V based SoC without budgeting CPU IP upfront.

“RISC-V is finding rapid adoption and creating high demand, especially in MCU level applications,” said Andes Technology President, Frankwell Jyh-Ming Lin. “Designers are seeking a small, efficient, and yet high performance-efficient commercial RISC-V core to construct their creative SoCs. Unlike open source RISC-V CPUs which are with limited features and lack of documents, and need to be verified by SoC designers first, users of the commercial-grade N22 can skip this time-consuming task which adds nothing to the value of their final SoC and instead spend their precious design resources on their true value added.”

“The N22 CPU is a small, 2-stage pipeline 32-bit RV32I/EMAC RISC-V CPU core, 16 or 32 general purpose registers, multiplier, atomic and compressed instructions. It also supports several unique and configurable features such as StackSafe™ for hardware stack protection, PowerBrake for efficient power management, CoDense™ for code size reduction on top of RISC-V C extension, and local memory and instruction cache for performance boost,” stated Andes CTO and Executive Vice President, Dr. Charlie Hong-Men Su. “The program also provides designers the option of 1-year support and a pre-integrated AHB platform with commonly used peripheral IPs, thus saving the time of sourcing and integrating these into their design. In addition, the RISC-V FreeStart can leverage the AndeSight™ IDE, a professional software development environment with over 15,000 worldwide installations, which has been available for free download.”

Availability

The RISC-V FreeStart program has been launched now. Anyone from industrial professionals to school students is invited to view and sign the online license agreement and download the N22 processor for evaluation purpose. The FreeStart also provides mass production program that allows industry, research institutes and academia to make commercial chips with running royalty or for research purpose but allow path of migration to mass production. Design teams can choose the optional technical support program available through Andes online e-service, which comes with an AHB platform RTL code for SoC integration. Please visit FreeStart.andestech.com or simply fs.andestech.com for more detail.

About Andes Technology

Andes Technology Corporation is a public listed company with well-established technology and teams to develop innovative high-performance/low-power 32/64-bit processor cores and associated development environment to serve worldwide rapidly growing embedded system applications.

The company delivers the best super low power CPU cores, including the new RISC-V series with integrated development environment and associated software and hardware solutions for efficient SoC design. Up to the end of 2018, the cumulative volume of Andes-Embedded™ SoCs has reached 3.5 billion with 2018 alone contributing over 1 billion.

To meet the demanding requirements of today’s electronic devices, Andes Technology delivers configurable software/hardware IP and scalable platforms to respond to customers’ needs for quality products and faster time-to-market. Andes Technology’s comprehensive CPU includes entry-level, mid-range, high-end, extensible and security families to address the full range of embedded electronics products, especially for connected, smart and green applications. From 2017, Andes expands its product line to RISC-V processors and provides a total solution in V5 family cores, including N22, N25F/NX25F, D25F, A25/AX25, and A25MP/AX25MP. 

For more information about Andes Technology, please visit

http://www.andestech.com

Continue ReadingAndes Technology Launches RISC-V FreeStart Program with its Commercial-Grade CPU N22

Andes Records a Rapid Growth of Design Wins in 2018 for Its New Family of RISC-V Processor Cores

Andes Signed 21 RISC-V IP Core Licenses in 2018 
Throughout the U.S. and Asia across a Wide Range of Applications

HSINCHU, TAIWAN – April 17, 2019 – Andes Technology Corporation, a leading supplier of small, low-power, high performance 32/64-bit embedded CPU cores, including a broad family of RISC-V cores, announced it achieved a record number of design wins for its new family of RISC-V processors during 2018. These include the 32-bit N25F/A25 and 64-bit NX25F/AX25. This represents a dramatic growth in the number of licenses signed soon after introduction of the RISC-V cores. Adoption of the RISC-V architecture is rapidly accelerating in China, spreading throughout the Asia Pacific region, and sweeping the U.S. Over a third of the 21 licensee agreements were signed in China and another third in Taiwan with the rest in the U.S., Korea and Japan. The wins are going into a wide range of application. Nearly half of the sockets are in artificial intelligence designs, where RISC-V plays an important role. Other applications adopting RISC-V include block chain, communications, fingerprint recognition, FPGA, IoT, security applications, and solid state storage devices. 

The rapid growth of RISC-V proves that increasing numbers of developers are adopting RISC-V architecture for their applications. Key to Andes successful lead in the RISC-V market was its rapid adoption of the RISC-V architecture. “We are thrilled at the customer acceptance of our RISC-V product line,” declared Andes Technology President, Frankwell Jyh-Ming Lin. “We joined the RISC-V Foundation as founding member because we were convinced of the commercial viability of the RISC-V CPU. In addition, the RISC-V architecture contains many of the fundamental elements already in our existing CPU IP product family. As a result, once the RISC-V foundation published the instruction set architecture (ISA), Andes was able to quickly develop our line of 32/64-bit RISC-V IP cores.” Owning to Andes’ rich experience in providing CPU IP, Andes achieved competitive advantage by meeting customers’ needs for RISC-V processor cores. “The advantage our IP has over competitive offerings is its ability to use special extensions already in existing Andes’ CPU IP to improve performance, plus other features such as PowerBrake, to reduce peak CPU power consumption; StackSafe™, to enhance system safety; and CoDense™ to reduce overall code size for a design.”

Andes RISC-V cores are based on AndesStar™ V5 architecture with single and double precision floating point support for high-precision data computations and MMU (Memory Management Unit) for Linux applications. In addition to the compactness, modularity and extensibility advantages of RISC-V ISA, Andes also provides customer-instruction extension capability to facilitate the design of Domain-Specific Architecture/Acceleration (DSA). “Andes’ RISC-V solution provides the capability to add custom extensions using our powerful Andes Custom Extension™ (ACE) tool,” stated Andes CTO and Executive Vice President, Dr. Charlie Hong-Men Su. “With ACE customers can add extensions specifically for their target applications to eliminate software bottlenecks and significantly improve runtime performance. While other CPU cores do not allow designers to add their own instructions to a CPU architecture, Andes provides COPILOT (Custom-OPtimized Instruction deveLOpment Tool) for ACE, which does the tedious but essential work needed to add a new instruction to a CPU ISA: creates the instruction’s RTL, its instruction set simulator, and its tool extensions—compiler, assembler, and debugger—automatically.”

As the recent popularity of RISC-V is rising among the CPU IP industry especially in China, the growth of RISC-V adoption and ecosystem is expected to rapidly accelerate.

Continue ReadingAndes Records a Rapid Growth of Design Wins in 2018 for Its New Family of RISC-V Processor Cores

Andes Technology Strengthens the RISC-V EasyStart Alliance to 15 ASIC Design Service Partners

HSINCHU, TAIWAN – March 18, 2019 – As the first public CPU IP company in Asia, specializing in low-power, high-performance 32/64-bit processor IP cores and SoC design platform, Andes Technology Corporation (TWSE:6533) created a RISC-V promotion program called the “EasyStart” in July, 2018. The goal of the RISC-V EasyStart program is to help Andes’ design service partners catch the emerging opportunity in RISC-V based SoC design and development. The expanding global alliance now has 15 members and is on the way to its target 20 members in the near future. 

The alliance in alphabetical order includes Alchip, ASIC Land, BaySand, CMSC, EE solution, INVECAS, MooreElite, PGC, SiEn (Qingdao) Semiconductor,Silex Insight, Socle , XtremeEDA and 3 unnamed partners. These companies cover foundry process technologies from 90nm to 10nm and some provide both SoC design and turn-key service. The alliance partners will use Andes qualified V5 RISC-V processor cores to provide their end customers total RISC-V design service solutions.

Andes has over ten years of professional experience in designing high-performance/low-power, 32/64-bit processor cores. Shipment of AndesCore™ embedded in customer SoCs in 2018 reaches one billion mark and the cumulative total volume surpasses 3.5 billion. One of RISC-V architecture’s merits is its extensibility. As a founding member of the RISC-V Foundation, Andes is dedicated to bringing its expertise in developing CPU processor cores to enhancing the RISC-V ISA. For example, the AndeStar™ V5, Andes’ fifth generation architecture, extends RISC-V ISA with features developed over the past 13 years. As the chair of the RISC-V P-extension (Packed SIMD/DSP) Task Group, Andes contributed its DSP ISA used in its successful D10 and D15 processors as the standard draft. As co-chair of Fast Interrupt Task Group, Andes is also proposing its extension to be part of the RISC-V standard. In addition, Andes is a major maintainer and contributor of the RISC-V open source software, including compilers, libraries, debuggers, and the Linux kernel. With its technical expertise and innovation, Andes is leading the empowerment of the RISC-V community. 

About the Andes V5 family processors
Andes V5 family processors include the 32/64-bit N25F/NX25F for general purpose or floating-point intensive applications, the A25/AX25 for Linux-based applications and the 32-bit N22, the smallest in the family for deeply embedded protocol processing and entry-level MCU applications. Based on AndeStar™ V5 ISA and Andes’ industry-recognized IP quality, these products have gained widespread attention thanks to their competitive performance, power, area, and RISC-V compliance. Andes also offers SoC platforms that contain the CPU core pre-integrated with the bus matrix and rich peripheral IP for these products. The platforms enable designers to jump start their SoC designs and ease migration and integration. 

To ensure the Andes V5 cores achieve their fullest performance, Andes also provides its highly-optimized compiler and production proven feature-rich IDE (integrated developer environment) to help customers achieve competitive advantage for their end products in the shortest time. Andes also provides its powerful Andes Custom Extension™ (ACE) tool COPILOT. The powerful features in COPILOT allows SoC design engineers, not familiar with processor design, to easily add customized instructions quickly to Andes processors to improve performance dramatically. Andes will release new product lines to address a wider range of applications and to continue its commitment to professional technical support to help customers create the most competitive products in the shortest time. 

The AndesCore™ based on RISC-V ISA has been widely adopted by customers in Taiwan, China, Korea, Japan and the US. Through the end of 2018, 21 licensee agreements have been signed, nearly half of which were targeting artificial intelligence design. Andes Technology will continue to expand its alliance with high-quality design service providers to provide end customers faster time-to-market.

Continue ReadingAndes Technology Strengthens the RISC-V EasyStart Alliance to 15 ASIC Design Service Partners

Andes Technology Announces RISC-V Single-core and Multicore Processors with DSP Instruction Set

Hsinchu, Taiwan. – March 12, 2019 – At the RISC-V Workshop Taiwan cohosted by Andes Technology today, Andes proudly announces the debut of its 32-bit A25MP and 64-bit AX25MP RISC-V multicore processors. The A25MP and AX25MP are the first commercial RISC-V cores with comprehensive DSP instruction extension. With the addition of cache-coherent multiprocessors and the DSP ISA based on the RISC-V P-extension draft Andes donated to the RISC-V Foundation, Andes brings powerful solutions to address the new market and further enriches its RISC-V lineup.

Multiple processor cores working in parallel empower applications such as artificial intelligence and Advanced Driver-Assistance Systems (ADAS) to boost performance of their computation intensive tasks significantly. Furthermore, hardware managed cache coherence simplifies software design considerably for systems with multiple CPUs. The A25MP and AX25MP support up to four CPU cores. They provide efficient cache coherence among private level-1 caches; include an optional shared level-2 cache; and support I/O coherence for bus masters without caches. Operating at over 1GHz in 28nm process with Linux symmetric multiprocessing (SMP) support, the A25MP and AX25MP raise the RISC-V processors to the next performance level and a wider market.

Many embedded applications processing digital signals such as voice, audio and image require efficient DSP instruction set as general-purpose baseline instructions are often not sufficient. As a founding member of the RISC-V Foundation, Andes responded to the popular inquiries for DSP capabilities in the RISC-V ISA by chairing the P-extension Task Group of the RISC-V Foundation, and donating its industry proven DSP/SIMD ISA to kick start the standardization effort. Andes’ new A25MP and AX25MP cores support the P-extension draft. Accompanying the DSP-capable processors are complete supporting tools including compiler, DSP libraries and simulator. Together they enable an over 7 times acceleration in the PNET for MtCNN (Multi-task Cascaded Convolutional Networks) face detection and alignment algorithm. They also provide an order of magnitude performance boost on CIFAR10 image classification benchmark for machine learning, which is a collection of images commonly used to train machine learning and computer vision algorithms.

“For over a decade Andes remains a major CPU IP vendor, and a leading supplier of RISC-V cores including the new N22-series and N25-series cores that serve the ever increasing demand for ultra-compact and high-performance RISC-V processors,” Andes President Frankwell Jyh-Ming Lin said. “Over 150 companies have licensed AndesCore™ processor IP and billions of electronic devices containing Andes CPU IP in a wide variety of applications have shipped globally.”

“The introduction of A25MP and AX25MP RISC-V multicore is a significant advancement for both Andes and the RISC-V community,” said Dr. Charlie Su, CTO and EVP of Andes Technology, “Built upon Andes’ successful processor solutions and solid development support, these powerful multiprocessor IPs with sophisticated DSP instructions as well as floating-point instructions mark the RISC-V architecture’s major step forward in the processor industry. It is truly exciting that Andes RISC-V solutions are being rapidly adopted by the industry since their introduction. We encourage the world to benefit from the developments pioneered by the RISC-V Foundation including Andes Technology.”

Along with the introduction of A25MP and AX25MP, their single-core versions, the previously released 32-bit A25 and 64-bit AX25 with Linux and floating-point support, are now upgraded with the DSP ISA. Also made available is the 32-bit D25F processor, which is an A25 without MMU and S-mode support to closely address DSP applications which do not need to run Linux. All these processor IP’s enjoys the same efficient baseline pipeline of the 25-series processors and the powerful ACE tools for custom instruction design.

For more information about the A25MP/AX25MP multicores, the upgraded A25/AX25, the D25F, and the latest developments of RISC-V P-extension DSP/SIMD ISA, please contact Andes Technology at http://www.andestech.com/.

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