Andes and SEGGER Partner to Deliver Professional Development Solutions for RISC-V

Hsinchu, Taiwan. – March 11, 2019 – Andes Technology Corporation (TWSE:6533), a founding member of the RISC-V Foundation and the leading supplier of 32/64-bit embedded CPU cores with solutions serving in excess of 1-billion diversified SoCs in 2018, and SEGGER Microcontroller, a leading supplier of software, hardware and development tools for embedded systems, today announced the availability of SEGGER powerful development solutions support for Andes RISC-V processor families.

Andes RISC-V processors are based on AndeStar™ V5 architecture, which maintains the full compatibility to RISC-V technology and thus inherits its compact, modular and extensible advantages. In addition, AndeStar™ V5 architecture brings Andes-extended features already proven in high-volume V3 AndesCore™ processors to be effective and beneficial for embedded applications with enhanced performance, code size and development support. Andes RISC-V cores include ultra-compact N22 for applications such as entry-level microcontrollers and deeply-embedded protocol processing, 32/64-bit N25/NX25 for high-speed control tasks, N25F/NX25F for floating-point intensive applications and A25/AX25 for Linux-based applications.

SEGGER’s professional libraries and tools for embedded system development are designed for simple usage and optimized for the requirements imposed by resource-constrained embedded systems. The J-Link debug probes, Ozone – the accompanying debugger – and Embedded Studio – the powerful cross platform C/C++ IDE (Integrated Development Environment) – are available to support embedded system developers to create their RISC-V based embedded systems. In addition SEGGER provides an RTOS, communication and security software to help developers design their systems without reinventing everything from scratch while benefitting from SEGGER’s more than 25 years of experience in the industry.

“Andes is determined to provide the best RISC-V solutions to help our customers design SoC exceeding their expectations. We understand that embedded software development is a major part of any SoC project.” said Dr. Charlie Su, CTO and Executive VP of Andes Technology. “With SEGGER’s industry-leading development tools support, the software designers can easily and quickly develop compact, efficient embedded applications that benefit from standard RISC-V features and Andes extensions.”

“With more than 25 years of experience in the embedded industry, we at SEGGER are The Embedded Experts and produce state-of-the-art development tools which simply work. We use our own tools for development and production to make sure, that we can deliver the highest possible quality to our customers”, said Alex Grüner, CTO of SEGGER. “We are pleased to support Andes RISC-V processors with our professional development solutions for easy development and faster time to market.”

For more information about Andes RISC-V processors, click http://www.andestech.com/markets.php.

For more information about SEGGER development solutions, click https://www.segger.com/.

About Andes Technology Corporation
Andes Technology Corporation is a public listed company with well-established technology and teams to develop innovative high-performance/low-power 32/64-bit processor cores and associated development environment to serve worldwide rapidly growing embedded system applications. In 2018, Andes-Embedded SoCs reach an annual run rate of over 1 billion mark with over 3.5 billion total cumulative units.
To meet the demanding requirements of today’s electronic devices, Andes Technology delivers configurable software/hardware IP and scalable platforms to respond to customers’ needs for quality products and faster time-to-market. Its comprehensive processor offerings include a wide range of performance with efficient control, data processing, extensible and security capabilities to address the diversified embedded electronic devices, especially for connected, smart and green applications. Since 2017, Andes incorporated RISC-V technology into its AndeStar V5 architecture and released a series of performance-efficient 32/64-bit V5 processors, including N22, N25/NX25, N25F/NX25F and A25/AX25. The powerful tool for Andes Custom Extension (ACE) enables flexible Domain-Specific Acceleration (DSA) for V5 processors, and takes performance efficiency to the next level. 

For more information about Andes Technology, please visit http://www.andestech.com/

About SEGGER Microcontroller
SEGGER Microcontroller is a full-range supplier of software, hardware and development tools for embedded systems. The company offers support throughout the whole development process with affordable, high quality, flexible and easy-to-use tools and components.
SEGGER offers solutions for secure communication as well as data and product security, meeting the needs of the rapidly evolving IoT.
SEGGER was founded in 1992, is privately held, and is growing steadily. Headquartered in Germany, with US offices in the Boston area and Silicon Valley, as well as distributors in all continents, SEGGER offers its full product range worldwide.

For more information about SEGGER Microcontroller, please visit https://www.segger.com/

Continue ReadingAndes and SEGGER Partner to Deliver Professional Development Solutions for RISC-V

Andes Technology Corp. Targets Deeply Embedded Protocol Processing and Entry-level MCUs With the New N22, the Smallest RISC-V Core in its V5 Family

N22 Delivers up to 3.93 CoreMark/MHz, in as little as 15K Gates with Highly Flexible Interfaces and Debug Support

HSINCHU, TAIWAN–Andes Technology Corporation, a leading supplier of small, low-power, high performance 32-/64-bit embedded CPU cores, including a broad family of RISC-V processors, announces the new N22 32-bit RISC-V CPU core to target deeply embedded protocol processing such as high-speed communication and storage, and entry-level MCU applications such as small IoT and wearable devices. The highly configurable N22 is the smallest in the Andes RISC-V family offerings in just 15K gates with minimum useful configuration settings, and yet delivers over 750MHz at 28nm in the worst case. In addition, the N22 provides an impressive 3.93 CoreMark/MHz, highly flexible system and memory interfaces and vector interrupt controller. In addition, a low pin count two-wire debug module can save SoC chip cost, and a pre-integrated MCU platform with frequently used peripherals can help speedup construction of various SoCs.

“CPU cores to serve today’s high-speed communications and storage markets must be able to do more than run at a high data rate,” declares Andes Technology President Frankwell Jyh-Ming Lin. “The protocol SoCs serving these markets are highly complex to meet widely diverse applications.  As a result, SoCs need to offer not only high bandwidth processing to accommodate the data rate, but also software based flexibility when new standards and protocols are adopted by the industry standards groups in these markets.  Furthermore, silicon costs dictate ultra-small gate counts to serve anywhere within the SoC design, especially when dozens of instances are needed. The N22’s high performance and compact design makes it very suitable to process on-the-fly protocol packets at high data-rate. ”

“The N22 is a 2-stage pipeline core with small gate count which can fit in entry-level MCU applications such as small IoT and wearable devices. It supports 16 or 32 GPRs (general purpose registers), optional branch prediction, hardware multiplier and divider, vector Interrupt Controller, and Andes V5 extensions,” stated CTO and Senior Vice President, Dr. Charlie Hong-Men Su.  “In addition to Andes’ professional development environment, the N22’s RISC-V RV32IMAC or RV32EMAC ISA compatibility opens up the full suite of compiler, debugger, ICE/trace probe tools from RISC-V Foundation’s rich ecosystem. The N22 leverages Andes’ long track record of CPU development, including the high-volume N7/N8 families with efficient short pipelines and many useful features such as StackSafe™ for hardware stack protection, CoDense™ for code size compression, and PowerBrake for power management.  Moreover, the new N22 will be available with a rich set of system level configuration options such as Physical Memory Protection (PMP), Platform-Level Interrupt Controller (PLIC), cache and local memories, private bus interface, and fast IO interface with 0-cycle latency.” 

Price and Availability 
The N22 pricing will be consistent with current Andes licensing and royalty business model.  The core will be available in February, 2019 for initial customer delivery.

Continue ReadingAndes Technology Corp. Targets Deeply Embedded Protocol Processing and Entry-level MCUs With the New N22, the Smallest RISC-V Core in its V5 Family

Andes Technology Records 1 Billion SoC Shipments in 2018 Based on Its CPU IP and 3.5 Billion Since Inception

HSINCHU, TAIWAN – February 14, 2019 – As the first public listed CPU IP company in Asia, specializing in low-power, high-performance 32/64-bit processor IP cores and SoC platform, Andes Technology Corporation (TWSE:6533) announced an extraordinary record of 1 billion annual SoC shipments containing its CPU IP in 2018. The cumulative SoC shipments surpassed 3.5 billion. Applications in which Andes CPU IP performs include AI and machine learning, audio, Bluetooth, gaming, GPS, MCU, sensor fusion, SSD controllers, touch screen and TDDI controllers, USB 3.0 storage, voice recognition, Wi-Fi, and wireless charger.

Andes President, Frankwell Lin declared, “The shipments of SoC embedded with Andes CPU cores have been experiencing remarkable growth from 430 million in 2016 to 590 million in 2017 and further to 1 billion in 2018 at an annual growth rates of 37% and 69%, respectively. This data demonstrate that Andes’ product development and service practice is solid and mature, and our comprehensive solutions and competitive technologies enable customers to enter their market with strong product offerings. Andes continues to focus on processor IP development to bring more and better products and solutions to market. As more and more customers start mass production of their SoCs, we believe the SoC shipment volumes and associated royalties of Andes IP will continue growing at the accelerating rate demonstrated up to now.”

“With the SoC challenges driven by ever-increasing and diversified product requirements in the market, Andes aims to become our customers’ ‘Trusted Computing Expert’ to help tackle their computing needs. We will continue leveraging our 13 years of experience in developing and supporting our own ISA to enhance our new V5 RISC-V processor series.  In the process, we will maintain compliance with the emerging open RISC-V architecture, while leading the RISC-V solution trend to become a world-class processor IP supplier!” President Lin said, “Going forward, Andes will actively assist customers in developing products in the emerging markets of AIoT, AR/VR, automotive, machine/deep learning, robotics, etc.

Dr. Charlie Su, Andes CTO and Senior Vice President, also stated, “Driving innovations is the motto of Andes R&D teams and the key to maintaining Andes products’ competitive edge. In addition to expertise in processor technologies, Andes continues to accumulate a rich, growing body of experience from providing technical support to over 150 customers. Expertise and experience are the reasons customers choose Andes over competitors. Andes Custom Extension™ (ACE) is a good example. Its powerful features allow SoC design engineers, not familiar with processor pipeline design, to easily add customized instructions to Andes processors to improve the performance dramatically in a short time. For ACE customers, the COPILOT tool not only generates RTL and toolchains, it can also generate verification patterns and cross-checking environment to greatly simplify designers’ tasks to verify the correctness of their instruction designs.”

During 2018, Andes Technology not only continued its support of V3 processors, it also introduced four new 32/64-bit V5 (RISC-V) processors, N25F/NX25F with floating point support and A25/AX25 for Linux applications, to accompany the fast-and-compact N25/NX25 for high-speed control tasks. Andes V5 processors have been licensed to many customers for applications in AI, communication, FPGA, security and storage. In 2019, Andes Technology plans new product line releases to address a wider range of applications. It will continue its high level of professional technical support to help customers create the most competitive products in shorter time.

For more information on Andes Technology and its products of low-power, high-performance 32/64-bit CPU IP cores, please visit www.andestech.com or contact sales@andestech.com.

Continue ReadingAndes Technology Records 1 Billion SoC Shipments in 2018 Based on Its CPU IP and 3.5 Billion Since Inception

Feature-rich RISC-V IDE Available for Free Download

Production-proven AndeSight™ Boosts RISC-V Development
HSINCHU, TAIWAN – January 30, 2019 – Andes Technology Corporation (TWSE: 6533), a founding member of the RISC-V Foundation and the leading supplier of 32/64-bit embedded CPU cores with solutions serving in excess of 3.5-billion SoCs covering a wide range of applications, today announced the free download of its AndeSight Integrated Development Environment (IDE) to accelerate software development for RISC-V based SoC. AndeSight IDE is a professional IDE based on Eclipse with many useful Andes add-on features, developed and widely used over the past 13 years, which provides an efficient way to develop embedded applications for RISC-V based SoC.

In an era of ever-changing embedded products, to pursue an easy, flexible design environment and to save efforts of hardware designers and software programmers, AndeSight integrates all environments for hardware and software from simulators, FPGA, to final SoCs to provide a complete software development solution. Empowered by AndeSight, RISC-V developers can run benchmarks and evaluate algorithm performance easily using a near-cycle accurate simulator. Based on Eclipse, AndeSight has many additional user-friendly features to help reduce development time. These include the following:

        ● Meta linker script editor
        ● Flash in-system-programming
        ● Virtual hosting
        ● Meta-file-based bit-field viewer for SoC registers
        ● Script-based RTOS awareness debugging
        ● Break and display on exceptions
        ● Function profiling
        ● Code coverage
        ● Function code size
        ● Stack size analysis

AndeSight also comes with a highly optimized compiler to deliver best-in-class performance and code density.

“Based on the successful experience in helping customers achieve cumulative shipments of more than 3.5 billion SoCs, AndeSight provides a professional embedded software development environment for RISC-V CPUs with its comprehensive and handy features.” said Dr. Charlie Su, CTO and Senior VP of Andes Technology. “With powerful AndeSight support, the software developers of RISC-V based SoC can deliver high-quality code with ease and speed their time-to-market”.

AndeSight for Andes RISC-V cores, N25/N25F, NX25/NX25F, A25 and AX25, is available for free download now. The free download version is a full-featured AndeSight with a three-month time limit. To explore AndeSight’s rich features, please visit AndeSight introduction page at http://www.andestech.com/en/products-solutions/andesight-ide/ and download page at http://www.andestech.com/en/support-downloads/andesight-ide-download/ for more details.

Continue ReadingFeature-rich RISC-V IDE Available for Free Download

Andes Custom Extension™ Further Accelerates Your High Performance RISC-V Processors

Hsinchu, Taiwan. -December 06, 2018 – Andes Technology today announced its newly-released AndeStar™ V5 CPU cores – N25/N25F, NX25/NX25F, A25 and AX25 – support the Andes Custom Extension™ (ACE) feature. The AndeStar™ V5 architecture is the result of RISC-V technology incorporated with Andes innovations based on rich experience in serving embedded processor IPs for over 10 years. The ACE feature enables embedded designers to add customized instructions on their Andes V5 CPU cores with ease.

RISC-V is an open processor instruction set architecture (ISA) standardized by the non-profit RISC-V Foundation. It is rapidly gaining popularity in many markets because of its compactness, modularity and extensibility. In addition to general-purpose usages, RISC-V specification encourages customized instruction extensions to facilitate the design of Domain-Specific Architecture/Acceleration (DSA) for applications such as Artificial Intelligence/Machine Learning, AR/VR, ADAS, and next generation storage and networking. Acceleration through customized instructions can boost application performance significantly while maintaining the programmability. Despite the huge benefits that may bring, however, most SoC teams find it difficult to add customized instructions. This is because designing new instructions requires major efforts and CPU talents to modify the existing processor hardware and associated software tools and make sure they work together.

Andes Technology fills this gap by providing the ACE design environment which greatly simplifies the steps to add instructions. By preparing a description file that describes instruction input/output interfaces and instruction semantics in C and a concise Verilog file implementing the RTL logic based on the given interfaces, designers can execute the Custom-OPtimized Instruction deveLOpment Tools™ (COPILOT) to generate the extended CPU and software toolchains in minutes.

The COPILOT tool is the key to the automatic creation of ACE instruction environment. It offloads all housekeeping RTL design tasks such as opcode selection, instruction decoding, operand mapping, input operand accesses, dependence checking and result gathering. Using ACE needs no expertise in processor pipeline design, thus minimizing the learning curve. Designers can then focus on the implementation of powerful functionalities rather than spend time figuring out how to interact with CPU pipeline.

The most powerful features of ACE are the constructs to define high level instruction semantics and enable the automatic RTL generation. For example, the vector construct allows developers to design a vector instruction as simple as its scalar counterpart, and the background construct enables parallel execution by allowing long latency ACE instructions to proceed in background. Designers can also use custom-defined registers (ACR) and memories (ACM) with arbitrary bit widths to have wide inputs and outputs processed by ACE instructions. These ACE features can contribute to significant performance improvements. COPILOT also facilitates verification process in addition to its usage on toolchain generation. It can generate verification patterns and cross-checking environment that help designers to verify the correctness of their instruction designs. 

“Using ACE is easy for designers who already know Verilog and C languages. With the powerful ACE constructs, richer functions can be implemented with fewer lines of code. ACE instructions not only accelerate applications by replacing a sequence of baseline instructions, but also reduce power consumption and code size,” said Dr. Charlie Su, CTO and Senior VP of Andes Technology. “By utilizing Andes highly-optimized V5 processor cores incorporated with effective ACE custom instructions that closely address application bottlenecks, you can greatly enhance their capabilities to reach high performance design goals”.

Andes Custom Extension™ for AndesCore™ N25/N25F, NX25/NX25F, A25 and AX25 is available for license now. To explore ACE’s full capabilities, please contact Andes Technology for more information.

Continue ReadingAndes Custom Extension™ Further Accelerates Your High Performance RISC-V Processors

Hex Five Adds MultiZone Security to the Andes RISC-V Cores on GOWIN FPGAs

SAN JOSE, USA – December 17, 2018 – Hex Five Security, Inc, the creator of MultiZone™ Security, Andes Technology Corporation and GOWIN Semiconductor Corp announced a collaboration to enable MultiZoneTM Security, the first Trusted Execution Environment for RISC-V on the Andes N(X)25 RISC-V Cores, which is part of 25-series, with the GOWIN GW-2A Family of FPGAs. 

Hex Five’s patent pending technology provides policy-based hardware-enforced separation for an unlimited number of security zones, with full control over data, code, interrupts and peripherals. MultiZone’s™ Configurator takes fully compiled and linked customer code and merges it with Hex Five’s nanoKernel to enable rapid adoption without any changes to hardware or customer code basis.

Andes 32-bit N25(F)/A25, and 64-bit NX25(F)/AX25 are versatile CPU cores compliant to RISC-V ISA that deliver over 3.5 CoreMark/MHz and 1.3 WMIPS/MHz for single precision floating point. Their common features include dynamic branch prediction, instruction and data caches, local memories, and Andes Custom Extension™ (ACE) to simplify instructions design for Domain-Specific Acceleration. All cores support User/Machine mode, while the A25/AX25 add Supervisor mode and MMU for Linux kernel and its applications. 

GOWIN’s GW2A Family is designed to offer the best-in-class performance cost ratio FPGA. With abundant logic, high-performance DSP resources and high speed I/O, the family is optimized for co-processing to offload the application processor on intensive computation tasks. The GW2A family is also the first FPGA with embedded pSRAM in the industry, which gives customers more usable device I/O.

“The Chinese market will be the first mass adopter of RISC-V,” said Dr. Charlie Su, CTO and Senior VP of Andes. “We’re happy to work with Hex Five to provide our customers a simple, robust security implementation that based on our RISC-V cores and comprehensive AndeSight™, an eclipse-based development environment and optimized toolchains to provide leading performance and reduced development time.”

“Increasingly, customers in China see security as a core requirement of their products,” said Jim Gao, Director of Solution Development, GOWIN Semiconductor. “With MultiZone Security, they can implement a robust security solution on our existing FPGAs without the need for new hardware, deep security expertise or even any changes to their toolset and workflow. This allows a customer to get to market fast, which is the goal of our FPGA solutions.”

“The cost of a robust security implementation on RISC-V is now negligible – the future of RISC-V is security by default.” said Don Barnetson, co-founder of Hex Five Security. “We’re very excited to enter the Chinese market with such strong partners and expand access to simple, robust security that any developer can implement.”

Hex Five, Andes and GOWIN Semiconductor demonstrated MultiZone™ Security at Andes RISC-V CON on Nov 13, 2018 at Andes RISC-V CON in Santa Clara, CA.  http://www.andestech.com/Andes_RISC-V_CON/

About GOWIN Semiconductor Corp
Founded in 2014, GOWIN Semiconductor Corp., headquartered with major R&D in China, has the vision to accelerate customer innovation world wide with our programmable solutions. We focus on optimizing our products and removing barriers for customers using programmable logic devices. Our commitment to technology and quality enables customers to reduce the total cost of ownership from using FPGA on their production boards. Our offerings include a broad portfolio of programmable logic devices, design software, intellectual property (IP) cores, reference designs, and development kits. We strive to serve customers in the consumer, industrial, communication, medical, and automotive markets worldwide.

For more information about GOWIN, please visit http://www.gowinsemi.com/

About Hex Five Security
Hex Five is the creator of MultiZone™ Security, the first trusted execution environment (TEE) for RISC-V. Hex Five’s patent pending technology provides policy-based hardware-enforced separation for an unlimited number of security domains, with full control over data, code, interrupts and peripherals. Contrary to traditional solutions, MultiZone™ Security requires no additional hardware, dedicated cores or clunky programming models. Open source libraries, third party binaries and legacy code can be configured in minutes to achieve unprecedented levels of safety and security. 

MultiZone™ Security is a free and open standard. Download it from the open source repository at https://github.com/hex-five

For more information visit https://www.hex-five.com/

Continue ReadingHex Five Adds MultiZone Security to the Andes RISC-V Cores on GOWIN FPGAs

IAR Systems and Andes collaborate to boost performance for RISC-V users

Establish partnership to provide powerful solutions based on Andes’ RISC-V technologies

Uppsala, Sweden and Hsinchu, Taiwan—November 29, 2018—
IAR Systems®, the future-proof supplier of software tools and services for embedded development, and Andes, the prominent CPU IP provider, announce that they have formed a partnership in order to deliver powerful development tools for Andes’ RISC-V-based solutions.

IAR Systems provides the C/C++ compiler and debugger toolchain IAR Embedded Workbench®. The toolchain offers leading code performance for size and speed, as well as extensive debug functionality with a fully integrated debugger with simulator and hardware debugging support. Since 1983, IAR Systems’ solutions have ensured quality, reliability and efficiency in the development of over one million embedded applications. The strong technology offering is accompanied by IAR Systems’ renowned technical support and services.

Andes Technology Corporation is a leading embedded processor intellectual property supplier. Since 2005, the company develops high-performance, low-power processors and their associated SoC platforms, and they have created a rich series of 32-bit embedded CPU core families with a record of more than 2.5 billion accumulated units of Andes-Embedded SoC shipped globally by end of 2017. Andes provides the RISC-V cores, AndesCore™ N25(F)/NX25(F) and A25/AX25, with AndeStar™ V5 instruction extension and leading Andes Custom Extension™ (ACE) instruction customization capabilities. The AndesCore families are being used for a wide range of smart emerging applications including satellite navigation, high-precision sensor fusion, advanced smart meters, smart wireless communication, networking, voice processing, ADAS, storage, and machine/deep learning. To further boost the performance in the target applications, and to ensure code density, Andes and IAR Systems collaborate to support the cores in IAR Embedded Workbench.

“Andes is moving heavily into RISC-V, and we are determined to support their efforts,” says Anders Holmberg, Chief Strategy Officer, IAR Systems. “By providing maximized code speed and minimized code size for Andes powerful RISC-V cores, we will create new possibilities to reduce time to market and ensure high quality applications based on Andes’ RISC-V ISA.”

“We are excited to partner with IAR Systems to bring new capabilities to the RISC-V community,” comments Dr. Charlie Su, CTO and Senior VP, Andes Technology Corporation. “Together, we will offer powerful solutions for Andes V5 extended ISA as well as ACE that will enable our customers to meet the demanding requirements of today’s electronic devices.”

Support for Andes cores will be provided in IAR Embedded Workbench for RISC-V. The toolchain is currently under development and the first version will be available in mid-2019. 

About IAR Systems

IAR Systems supplies future-proof software tools and services for embedded development, enabling companies worldwide to create the products of today and the innovations of tomorrow. Since 1983, IAR Systems’ solutions have ensured quality, reliability and efficiency in the development of over one million embedded applications. The company is headquartered in Uppsala, Sweden and has sales and support offices all over the world. Since 2018, Secure Thingz, a provider of advanced security solutions for embedded systems in the IoT, is part of IAR Systems. IAR Systems Group AB is listed on NASDAQ OMX Stockholm, Mid Cap. Learn more at www.iar.com.

About Andes

Andes Technology, the first CPU IP supplier in Asia, has been developing innovative high-performance/low-power 32/64-bit processors and associated SoC platforms since its establishment in 2005. Its powerful CPU lineup has achieved design wins in numerous embedded applications across the world, making a cumulative record of over 2.5 billion SoC shipments containing Andes IP up to 2017. Andes is a founding member of the RISC-V Foundation and also the first mainstream CPU vendor adopting the RISC-V open ISA. For more information please visit: www.andestech.com.

Continue ReadingIAR Systems and Andes collaborate to boost performance for RISC-V users

Andes Announces over 1.2 GHz RISC-V Cores Series at 28nm: A25/AX25 and N25F/NX25F

Andes Technology Corporation (TWSE:6533), a founding member of the RISC-V Foundation and the leading Taiwan-based supplier of 32/64-bit embedded CPU cores with solutions serving in excess of 2.5-Billion SoCs covering a wide range of applications, today announced the availability of the latest four members of the AndeStar™ V5 high efficiency processor series: (1) the AndesCore™ A25/AX25, perfect for Linux-based applications such as UAV(Unmanned Aerial Vehicle), smart wireless communication, networking, video processing, ADAS (Advanced Driver Assistance Systems), storage, data center, and machine/deep learning; and (2) the AndesCore™ N25F/NX25F, that can be used for a wide range of floating-point intensive applications including advanced motor control, satellite navigation, high-precision sensor fusion, and advanced smart meters.

The A25/N25F are 32-bit CPU IP cores, and AX25/NX25F are 64-bit ones. All of them are capable of operating over 1.2 GHz at the worst-case corner of TSMC 28nm HPC+ process, delivering over 3.5 CoreMark/MHz, and 1.3 MWIPS/MHz for single precision floating point. Their common features include dynamic branch prediction, instruction and data caches, Local Memories for low-latency accesses, L1 memory ECC for soft error protection, and Andes Custom Extension™ (ACE) to greatly simplify instructions design for Domain-Specific Acceleration (DSA). All cores support User/Machine Mode (U/M mode) while the A25/AX25 add Supervisor Mode (S-mode) and memory management unit (MMU) to run Linux kernel and its applications. In the floating point side, the N25F/NX25F support IEEE754-compliance with either single precision or single/double precisions. Andes further extends floating-point support to half precision for applications such as machine learning, where loads/stores automatically convert 16-bit half-precision data to/from single precision data. The A25/AX25 also optionally support all the floating-point features mentioned above. All processors are offered in human-readable and tool-friendly Verilog RTL and with a GUI tool for designers to flexibly choose their final configurations.

“Andes adopted RISC-V as the subset of its fifth generation architecture, the AndeStar™ V5, and brings it to the RISC-V community,” Dr. Charlie Su, CTO and Senior VP of Andes Technology commented, “The A25/AX25 and the N25F/NX25F are versatile processors with a 5-stage pipeline and RISC-V compliant ISA (RV-IMAC[FD]). All 25-series processors include Andes-enhanced Platform-Level Interrupt Controller (PLIC) with vectored interrupt dispatch and priority-based preemption for efficiently serving various types of system events, and can be pre-integrated with 64-bit AXI or 64/32-bit AHB bus platforms. They also bring to RISC-V common cache features for embedded systems such as finer-grained cache management, write-back and write-through modes, and uncached accesses. In addition, PowerBrake, QuickNap™ and WFI (Wait for Interrupt) operation together enable various power modes to address application needs; JTAG and 2-wire interfaces are available for debug and trace support; the StackSafe™ protects the software stack from overflow and underflow; and the Andes’ patented CoDense™ enhances code density on top of RISC-V C-extensions. It also supports misaligned memory accesses directly in hardware, which is good for porting existing software from ARM and x86; without it, more than 100 cycles may be required in the exception handler. They have been selected by our customers for their exceptional performance/power, flexible configurations, highly optimized compiler and comprehensive development tools. We are also engaged with 3rd party partners to provide more development tools, IPs, and runtimes, including fast system simulators, security subsystems, SoC analytics, tracer and debugger, software stacks and more. “

The V5 AndesCores inherit the compact, modular and extensible advantages from the RISC-V technology and also enjoy its fast-growing ecosystem. In addition to full compatibility to RISC-V technology by supporting its standard instructions, AndeStar V5 architecture brings Andes-extended features already proven in high-volume V3 AndesCores to be effective and beneficial to embedded applications.

Andes is a major contributor to the RISC-V open source software, ranging from GCC and LLVM compilers, libraries, debuggers, to U-Boot and the Linux kernel and its key components. In addition, Andes also plays a key role to grow the RISC-V architecture, acting as the chair of ISA P-extension (Packed DSP) Task Group and the co-chair of Fast Interrupt Task Group. Andes is committed to taking RISC-V mainstream by helping accelerate the ecosystem growth together with partners.

 

Continue ReadingAndes Announces over 1.2 GHz RISC-V Cores Series at 28nm: A25/AX25 and N25F/NX25F

GOWIN Semiconductor Licenses Andes Technology RISC-V CPU Core For Its Arora® GW-2A FPGA Family Products

Andes Technology Provides GOWIN Standard RISC-V CPU ISA, 
Plus Enhanced Features for Performance, Reliability, Program Code Size and Power Consumption

HSINCHU, TAIWAN & GUANGZHOU, CHINA – October 01, 2018—Andes Technology Corporation, the leading Asia-based supplier of small gate count, low-power and high performance 32/64-bit embedded CPU cores, announces that GOWIN Semiconductor has licensed Andes Technology’s RISC-V CPU core for its Arora® GW-2A FPGA family of products. Besides the standard RISC-V ISA, the Andes Technology RISC-V CPU comes with additional features to improve performance, reliability, program code size and power consumption reduction.

“Adding the Andes RISC-V to our Arora Family of FPGA’s provides fast time to market for engineers wanting to implement a design using the RISC-V CPU,” said Scott Casper, Director of Sales for GOWIN’s Americas Region. “The CPU core can be implemented in a relatively small number of FPGA logic elements thus providing additional capacity for the engineer’s logic design.  Having Andes as a partner has enabled GOWIN to quickly supply customer demand for this popular CPU ISA.”

“We are thrilled that GOWIN has chosen the Andes RISC-V CPU core for their Arora® GW-2A FPGA Family products,” said Vivien Lin, Vice President of Sales Andes Technology USA Corp. “Demand for the Andes RISC-V CPU offering is growing and having GOWIN offering an FPGA version combined with the Andes RISC-V  Eclipse-based development environment provides designers a fast track to develop their offering.”

About GOWIN Semiconductor Corp.
Founded in 2014, GOWIN Semiconductor Corp., headquartered with major R&D in China, has the vision to accelerate customer innovation world-wide with their programmable solutions. GOWIN focuses on optimizing their products and removing barriers for customers using programmable logic devices. GOWIN’s commitment to technology and quality enables customers to reduce the total cost of ownership from using FPGA on their production boards. GOWIN’s offerings include a broad portfolio of programmable logic devices, design software, intellectual property (IP) cores, reference designs, and development kits. GOWIN strive to serve customers in the consumer, industrial, communication, medical, and automotive markets worldwide. For more information about GOWIN, please visit www.gowinsemi.com.

About Andes Technology Corporation
Andes Technology Corporation was founded in Hsinchu Science Park, Taiwan in 2005 to develop innovative high-performance/low-power 32/64-bit processor cores and associated development environment to serve worldwide rapidly growing embedded system applications. The company delivers the best super low power CPU cores, including the rising star RISC-V series with integrated development environment and associated software and hardware solutions for efficient SoC design. Up to the end of 2017, the cumulative amount of SoCs containing Andes’ CPU IP reaches 2.5 billion. To meet the demanding requirements of today’s electronic devices, Andes Technology delivers configurable software/hardware IP and scalable platforms to respond to customers’ needs for quality products and faster time-to-market. Andes Technology’s comprehensive CPU line includes entry-level, mid-range, high-end, extensible and security families to address the full range of embedded electronics products, especially for connected, smart and green applications. From 2017, Andes expanded its product line and provides a total solution of RISC-V, the RISC-V series as V5 families processors cores include 32/64-bit N25/NX25 for general purpose, N25F/NX25F for floating-point intensive applications and A25/AX25 for Linux-based applications. For more information about Andes Technology, please visit http://www.andestech.com/.
 

Continue ReadingGOWIN Semiconductor Licenses Andes Technology RISC-V CPU Core For Its Arora® GW-2A FPGA Family Products

Andes Technology Corporation and XtremeEDA Corporation Cooperate to Develop Joint Design Wins on Emerging RISC-V Designs

Andes to Offer Its Low-Power, High Performance CPU Cores, Including New RISC-V IP;
XtremeEDA to Provide Its Front-end IC Design Expertise to Reduce Designers’ Time to Market
 

Andes Technology Corporation, the leading CPU IP supplier of small, low-power, high performance 32/64-bit embedded CPU cores, and XtremeEDA Corporation, a leading North American provider of front-end design and verification services for the semiconductor industry, today announced they will cooperate to develop joint design wins to benefit both companies. Andes will provide Its low-power, high performance CPU cores, including the first RISC-V core from a public semiconductor company; XtremeEDA will provide experienced front-end design and verification services, thus collectively reducing designers’ time to market.

“We are excited to be joining forces with XtremeEDA to provide our customers CPU IP and design resources they may not possess internally,” said Emerson Hsiao, Senior Vice President of Sales and Technical Service at Andes Technology Corporation USA. “In today’s embedded systems-on-chip (SoC) market, an increasingly important variable in how chips are designed and produced is time to market. A new start-up may have a great architectural specification but may lack the team, design tools, and IP needed to convert the design idea into a chip. In addition, many cannot afford the high cost for design verification.  Together XtremeEDA and Andes can offer its customers access to a design and verification team and a library of IP to support the Andes core that will provide reduced time to market for their unique design.”

“Andes represents a great supplement to our own sales and marketing effort,” said Chris Raeuber, XtremeEDA’s Director of Engineering, US. “As a major CPU core supplier in Asia, Andes has great market insight into the new designs going on in that region and they are bringing that knowledge to the U.S. They are identifying start-ups with unique new SoCs targeting emerging markets that need front-end and verification engineering resources, such as what we offer.  Together, we provide our mutual customers a means of rapidly getting their designs into silicon.”

Complementary Strengths
One service Andes provides its customers is an FPGA based version of its processor IP on a reference platform including the new RISC-V IP core. Prospects can evaluate the Andes core using the reference board. In many instances, once a prospect becomes a customer, he may decide to use a design services supplier to take the FPGA implementation and convert it into an SoC chip design. Having XtremeEDA, who is familiar with the Andes reference platform, to convert the FPGA implementation to an SoC chip design greatly shortens the customer’s time to market.

About XtremeEDA Corp.
Founded in 2002, XtremeEDA is a North American based provider of front-end design and verification services for the semiconductor industry.  Our team is unparalleled – with employees averaging 20+ years of semiconductor industry experience and expertise that spans most major sectors. Our business approach emphasizes enduring and transformational relationships to employ creative solutions that enable extraordinary results for all stakeholders. For more information, please visit https://www.xtreme-eda.com

Continue ReadingAndes Technology Corporation and XtremeEDA Corporation Cooperate to Develop Joint Design Wins on Emerging RISC-V Designs