Andes Technology Corporation Announces Quick-Start Design Package That Significantly Reduces Time to Market of SoC Designs

Solution Reduces the Time Consuming and Error Prone Task of Creating and Verifying Glue Logic to Integrate Disparate Elements of a SoC Design

【Hsinchu, Taiwan.】 Andes Technology Corporation, the leading Asia-based supplier of small, low-power, high performance 32-bit embedded CPU cores, today announced the Quick-Start Design Package, a complete solution that significantly reduces time to market for SoC designs. The package includes the new AndesCore™ N650 CPU IP, AndeShape™ AE100 Platform IP, and AndeSight™ IDE software development environment. The new compact N650 CPU provides the performance-efficiency needed for entry-level SoC, and the new Platform IP offers several highly-optimized peripherals and the bus fabric that SoCs require to surround and enable customer logic. By pre-integrating and pre-verifying processor, fabric, and peripherals, the package jump-starts customer’s SoC projects with a solid foundation and reduces custom glue logic design teams need to create. Instead of hardwired control logic, customers can use software created with AndeSight™ IDE to debug the SoC and control the various peripherals.

“Time-to-market is a major concern for every SoC design and one task that slows a design progress is writing RTL code for developing standard IP blocks, integrating them, and spending 70 percent additional effort in verification,” said Frankwell Jyh-Ming Lin, President of Andes Technology Corp. “The Quick-Start Design Package provides an optimized plug and play solution that saves effort developing common functions that are not providing any significant added value to their final design. CPU based system using software to control the peripheral elements reduces risk for SoC designs by eliminating the need to hardwire everything.”

“By running control software on the new Andes N650 CPU IP, design teams reduce their risk considerably and shorten their silicon development schedule,” said Charlie Hong-Men Su, Ph.D., Andes Technology CTO and Senior Vice President of R&D. “For example, it’s a simple software revision to change the configuration of PCIe, DDR boot sequence, and other functions post-silicon. In addition to facilitating software development and optimization, the AndeSight™ IDE allows access to the entire system for chip-level debugging through the JTAG interface. By re-using the production-quality processor and peripheral controllers, and extensible bus fabric, the Quick-Start Design Packagereduces design teams’ risk of a silicon respin.”

About the Quick-Start Design Package Solution
The individual elements of the Quick-Start Design Package—new AndesCore™ N650 CPU IP, AndeShape™ AE100 Platform IP, and AndeSight™ IDE software development environment—come with their own unique features. The new N650 CPU core is a 3-stage pipeline architecture with 16 general-purpose registers and multiply and divide instructions. The core delivers 25 percent better DMIPS/MHz performance and 40 percent better DMIPS/mW power efficiency than its competitive counterpart in the TSMC 90LP process.

The N650 CPU IP core has memory mapped I/O, a 32-bit wide AHB-Lite bus, up to 32 vectored interrupts, 4-priority nested interrupts, and power management instructions—essential for power sensitive designs. The core comes with Embedded Debug Module, 2-wire Serial Debug Port and up to 8 breakpoints/watchpoints.

The new AE100 Platform IP features a new AHB Configurable Fabric with 24-bit address width and 32-bit data width. It supports up to 8 AHB masters, up to 30 AHB slaves and up to 31 APB slaves. Components of the fabric include AHB-Lite master multiplexer, AHB-Lite decoder and AHB-to-APB bridge. Other peripherals included are a Low-latency RAM Bridge, general purpose I/O (GPIO), watchdog timer, programmable interval timer and UART.

The AndeSight Eclipse-based IDE provides a fully functional Andes C and C++ integrated development environment that enables managed build system. It comes with a profiler, code coverage, code size analysis, chip profile, in-system programming, and advanced debugging. The tool chain includes compiler, assembler, linker, loader, libraries, and debugger. Also provided are a core simulator, pre-defined models of AndeShape™ SoC platform, and external plugin APIs.

Availability
The Quick-Start Design Package will be available the third quarter of this year. The Andes Quick-Start license includes the following:

  • AndesCore™ N650 CPU IP
  • AndeShape™AE100 Platform IP
  • AndeSight™ IDE Software Development Environment

Also available is either a full-featured ADP-XC7 or a compact Corvette F1 (Arduino-Compatible) optional development board along with Andes High-value service and support.

Continue ReadingAndes Technology Corporation Announces Quick-Start Design Package That Significantly Reduces Time to Market of SoC Designs

Andes Technology Corporation and Acer BYOC™ Announce Inter-Platform Support on Internet-of-Things Cloud Solutions for SoC Design

Andes Technology and Acer BYOC’s Efforts Will Enable IoT SoC Designers to Empower Their Products with Cloud Computing Capabilities Through Andes’ Knect.me™ Ecosystem

【Hsinchu, Taiwan】Andes Technology Corporation, the leading Asia-based supplier of small, low-power, high performance 32-bit embedded CPU cores, and Acer BYOC™ (Build Your Own Cloud™) today announced plans to support each other’s Internet-of-Things cloud service solutions for SoC Design. Andes and Acer BYOC will each develop technology offerings that will enable SoC engineering design teams to build IoT SoCs with Acer cloud services using Andes Knect.me ecosystem resources. Andes will support Acer BYOC’s open platform and help expand Internet-of-Beings cloud ecosystem to the level of IC and SoC design. Acer BYOC will grow the vertical coverage of Andes’ CPU IP and IoT Knect.me ecosystem on their expanding cloud service platform.

“Both Acer and Andes offer complementing IoT solutions to the global market,” said Maverick Shih, President of BYOC Business Group at Acer Inc. “By offering inter-platform compatibility, we hope to create a mutually beneficial ecosystem for our joint customers.”
 “We admire how Acer has studied the progress of the IoT market trend over the long-term and devoted itself early on to building up cloud technology,” Frankwell Jyh-Ming Lin, President of Andes Technology Corporation, stated. “Our collaboration with Acer BYOC will enable Andes customers that design hardware and develop software for IoT SoCs the convenience of obtaining cloud service solutions plus underlying building blocks from Knect.me, our IoT ecosystem providing open-source and commercial solutions for modern connected devices based on the highly performance-efficient AndesCore™ processors. Customers will derive great benefit through this technology and business relationship.”

Cloud Service Platform and IoT Computing
Emerging services and innovative applications are raised by the development of ubiquitous computing and IoT devices. Equipped with sensing, connectivity, and intelligence, connected IoT devices change the computing paradigm. Legacy resources, such as storage and computation, are migrating from computing devices to the cloud for emerging networked applications. In addition to storage capacity and computing power, SoC designers for IoT applications also face the daunting task of integrating silicon intellectual property and software stacks as well as easy access to cloud services to complete real world usages of the IoT computing. The example of a fitness wearable illustrates how the cloud becomes a component of an SoC design. The SoC controls an intelligent sensor, but the cloud provides the sensor output.

The challenge is to build both device and service infrastructure. The inter-platform support of Andes and Acer BYOC combines the market proven elite software stack and hardware platform from Andes Knect.me ecosystem with the cloud service open platform from Acer BYOC. The Acer BYOC platform provides modular services such as music, file storages, media and document applications, and it also allows developers to rapidly bring new and innovative applications to IoT devices. By introducing such a flexible cloud platform on top of the rich device hardware-software framework, Andes and Acer BYOC enable developers to quickly bring smart connected applications to reality.

Continue ReadingAndes Technology Corporation and Acer BYOC™ Announce Inter-Platform Support on Internet-of-Things Cloud Solutions for SoC Design

Andes Technology Corporation Achieves 10,000 Installations of Its AndeSight™ Integrated Development Environment

Demonstrates Growing Market Adoption of Andes Powerful Cores which Minimize Manufacturing Costs, Reduce Power Requirements and Speed Time to Market

【Hsinchu, Taiwan】 Andes Technology Corporation, the leading Asia-based supplier of small, low-power, high performance 32-bit embedded CPU cores, today announced that it has achieved 10,000 installations globally of its AndeSight™ Eclipse-based integrated development environment (IDE). The powerful AndeSight IDE, which supports the entire range of AndesCore™ embedded CPU IP cores, enables Andes Technology’s customers to achieve minimum code size as well as highly reliable software code, while reducing customers’ time to market.

“AndeSight, with its complete and highly efficient features, has helped our customers to achieve cumulative shipments of over 1.4 billion SoCs,” stated Andes Technology Corporation President, Frankwell Jyh-Ming Lin. “This volume testifies to both the quality and adoption of AndeSight. Since AndeSight’s introduction, Andes Technology has continuously incorporated customers’ experiences, simplified development flow, and included new technology development, to provide superior software tool to the market. In the future, Andes Technology will continually enhance AndeSight to improve ease of use; to provide broad support of hardware, software, and system layers; and to boost higher efficiency and optimized code. In this way we will enable our customers to provide an even better product and service.”

“AndeSight implements a highly efficient compiler,” stated Charlie Su, Ph.D. Andes Technology Corporation CTO and Senior Vice President of R&D. “Across numerous applications, customers have found that our compiled code delivers best-in-class performance and compactness. Besides program development, code upgrading, and debugging, AndeSight also provides numerous advanced features. These include code coverage analysis, function profiling, performance meter, and a simple interface for customers to hook up their SoC-dependent GUI. With its rich features and friendly user interface, AndeSight has gained widespread user adoption. Today’s announcement of AndeSight reaching a 10,000-installation represents AndeSight has been used by more than 30,000 engineers, this milestone shows strong market endorsement of the stability and popularity of AndeSight. AndeSight serves both IC design houses and system companies, while enabling the latter to facilitate their market development.”

About AndeSight
Andes Technology began offering AndeSight in 2007. In 2015, the company released the latest AndeSight version 2.1.0, which includes four editions: STD, MCU, RDS and Lite. The STD edition supports the entire series of Andes Technology CPUs with functionality designed for high-end applications in the global SoC market. The STD edition’s Linux debugging features are well suited to the AndesCore D10, N10, and N13 cores. The MCU edition is designed for microcontroller development. It supports AndesCore N7, N8, E8, S8 and N9. The RDS edition is based on MCU edition but targeted at software developers at downstream customers of Andes Technology’s IC design company customers.

The Lite edition is a compact and free IDE targeting IoT and wearable applications. It can be downloaded from the knect.me™ website and is ideal for software evaluation. In addition, Andes Technology also collaborates with academia to provide AndeSight for uses in embedded system training courses, IoT applications, and SoC system. Through this collaboration program, Andes Technology aims to engender more software developers familiar with the AndeSight IDE and the AndesCore CPU families.

Continue ReadingAndes Technology Corporation Achieves 10,000 Installations of Its AndeSight™ Integrated Development Environment

Wave Semiconductor Selects Andes Technology for Embedded Core Wave to use N9 5-stage pipeline CPU Core

Andes’ Ease of SoC IP Integration, High Performance and Low Power Consumption 
All in a Compact Silicon Footprint Contributed to Winning the Business

【 San Jose, Calif.】– November 11, 2015 – Andes Technology Corporation, the leading Asia-based suppliers of small, low-power, high performance 32-bit embedded CPU cores, today announced that Wave Semiconductor (www.wavesemi.com) has licensed Andes low power, N9 32-bit, 5-stage pipeline CPU core and Andes AE210P peripherals for a new chip design. Wave selected the Andes core to provide boot–time configuration and continuous monitoring of Wave’s SoC operation. The ease of integrating the Andes N9 and peripherals into its larger SoC design, the native AXI4 support, high performance at low power consumption, and small silicon footprint contributed to Wave’s decision.

“We are pleased with our choice of the Andes N9 CPU core for our next SoC design,” said Richard Terrill, Vice President of Marketing at Wave Semiconductor. “We needed a small but powerful CPU to manage critical tasks at power-up boot and on-going observation of chip operation. The N9’s programming tools and support of the AXI bus interface fit our requirements nicely.  Its straightforward synthesis made for integration into our larger design and its small silicon footprint provided an added bonus.”

“Andes is thrilled that Wave Semiconductor chose our N9 CPU core for their new SoC design,” said Frankwell Lin, President of Andes Technology Corporation. “The N9 delivers high performance in a small gate count and on a low power budget. Its ability to provide low-latency vectored interrupt makes it very efficient for high performance real time monitoring. The N9’s ability to mix 16- and 32-bit instruction format enables compact code and the five-stage clock-gated pipeline contributes to the core’s 3.43 CoreMark/MHz performance, while its power management instructions conserve power.”

About Wave Semiconductor
Wave is a systems startup that has developed a low power, high-performance data flow computing platform to accelerate critical applications such as machine learning (CNN/DNN/AI), national/cyber security, unstructured search and big data analytics. Wave is developing a family of compute acceleration hardware ranging from OCP mezzanine to 1U appliances, all based on their proprietary Byte-Fabric™ programmable SOCs. By placing special emphasis on low-power computing, Wave offers best-in-class performance as measured in operations/Watt. The company is venture-backed (Tallwood and Southern Cross) and staffed with a cadre of industry veterans and entrepreneurs.
www.wavesemi.com

About Andes Technology Corporation
Andes Technology Corporation is a leader in developing high-performance/low-power 32-bit processors and its associated SoC platforms to serve the rapidly growing embedded system applications worldwide. The company’s broad and deep technical expertise in microprocessor, system architecture, operating system, software tool chain development, and SoC VLSI implementation enables designers to shorten their time-to-market with quality designs. In addition, Andes’ innovative configurable platform solution allows design teams to construct unique system architecture and hardware/software partitioning to achieve the optimal SoC.  For more information visit http://www.andestech.com.

 

Continue ReadingWave Semiconductor Selects Andes Technology for Embedded Core Wave to use N9 5-stage pipeline CPU Core

Andes Technology Corporation Launches New DSP+CPU Core Offering 134 Percent Higher Performance than Competing Alternatives for Low-Power SoC Designs

AndesCore™ D1088 CPU+DSP Combination Delivers Better Performance, Using Less Power with Half the Code Size of Competitive Offerings

【HSINCHU, Taiwan】Andes Technology Corporation, the leading Asia-based supplier of high-volume, low-power 32-bit embedded CPU cores, today announced the D1088, a 5-stage pipeline processor with integrated DSP offering 130 SIMD (single instruction, multiple data) instructions. When implemented in a 90nm low power process, the D1088 delivers 588 DMIPS, 134% higher than competing offerings. Measured using the popular Whetstone floating-point benchmark, the D1088 achieves 92% better performance. When running popular and comprehensive (over 200) DSP libraries, the D1088 is 116% faster with half the code size. Even with the above advantages, the D1088 still achieves smaller die area and less power per MHz than competing offerings.

“We’re proud of the results achieved with the D1088 DSP+CPU core,” said Dr. Charlie Su, Chief Technology Officer and Senior VP of R&D at Andes Technology Corporation. “With the increasing numbers of designs performing signal processing for smart sensors, image processing, motion detection, audio and video, the D1088 will provide a wide range of benefits, including better compute performance and power savings, as well as additional functionality. The D1088 easily interfaces with both AHB and AXI bus for simplified use in SOC devices. It comes with an optional memory management unit to support the Linux OS and an optional memory protection unit to support real time operating systems (RTOS).”

About the D1088
Tightly integrated Integer and DSP processor architectures are not new, but most were designed for applications where power was not as much a constraint as it is today. The new D1088 was designed with low power in mind. It contains functionality to enhance efficiency and reduce application code size to lower both power and cost. For example, to significantly boost the computational efficiency in matrix, filtering, Fourier Transform, and statistics functions, it can execute 4-way 8-bit, or 2-way 16-bit SIMD instructions in a single-cycle latency. In addition, for multimedia applications, the D1088 also supports 64-bit add, subtract, and multiply mixed computation.
For voice application, the D1088 offers left shift, right rounding and shift, most significant word, 32×32 multiply and specially designed 32-bit instructions to replace the lengthy 64-bit computation. To reduce code size and increase efficiency, the D1088 provides a Zero Overhead Loop instruction to offload loop branching.  To enhance parallel computational capacity, the D1088 provides left and right shift, minimum, maximum, and absolute value, besides traditional SIMD instructions such as add, subtract, and multiply.

Availability
D1088 is available immediately for customer uses and is fully supported by AndesSight™ Integrated Development Environment (IDE) tool chain.

Continue ReadingAndes Technology Corporation Launches New DSP+CPU Core Offering 134 Percent Higher Performance than Competing Alternatives for Low-Power SoC Designs

Zinitix BT541 Touch Screen Controller Uses Andes N968A

Fabless chip giant Zinitix, based in Yongin, South Korea, has licensed the AndesCore N968A-S CPU IP for its Progressive Capacitive(PCAP)Touch Screen Controller BT541.

Zinitix BT541 leverages the AndesCore N968A’s high performance and small gate count to provide the advanced PCAP functionality found in today’s smart phone touch panel controllers: multi-touch capability, gesture recognition, and touch accuracy. The Zinitix BT541 has been incorporated into the worldwide mobile phone industry supply chain.
According to HIS Inc., the capacitive touch controller IC market is forecast to double in size to $2.8 billion in 2017, from $1.4 billion in 2012, growing at a compound annual growth rate of 14.6 percent during the period.

The El Segundo, Calif. based market research firm declares capacitive touch technology is leading the growth.” In the past eight years, it has been steadily advancing in many areas including touch panel structure, its materials, and the manufacturing process. Along with this, the market for touch controller lCs, one of the key components that determine the touch screen panel’s performance, has also experienced growth.”

＂We are thrilled that Zinitix selected Andes from among our competitors for their BT541 fourth generation capacitive touch screen controller,＂ said Frankwell Lin, President of Andes. ” We look forward to continue enabling Zinitix to achieve their goal of becoming a global system IC leader. Korea is one of the most important markets for Andes.

In the future, Andes will aggressively promote its entire range of processors, the N7, N8, N9, N10, and N13, to provide SoC designers in Korea a wider selection of processor cores.＂

AndesCore N968A contributes to the cost/performance advantage of Zinitix’s BT541 to enable its success in the highly competitive PCAP touch screen market. Geoff Walker, Senior Touch Technologist, Intel Corp. places Zinitix in the top 15 PCAP controller suppliers worldwide.(＂Fundamentals of projected-Capacitive Touch Technoligy,＂ p.55)the N968A AndeStar™ V3 instruction set architecture adds 38 instructions to achieve superior system performance, minimum code size, and the lowest power consumption among competitive alternatives.

Zinitix Co., Ltd. Aims To Be the Global System IC Leader
Zinitix Co.is a fabless semiconductor enterprise specializing in developing world class system integrated circuits began in business nearly 20 years ago.

Since its founding, Zinitix has been invested heavily in innovative research and development. Today, Zinitix is high volume production of a wide variety of system ICs; touch controller ICs, auto focus driver ICs, haptic driver ICs, and motor driver ICs. Designed into smart phones, tablet PCs, laptop PCs, home appliances, and automotive applications, Zinitix products provide customers and markets epoch-making technology such as 1-layer touch and one chip auto-focus. Through creative R&D and leading technology, Zinitix’s Goal is become a global system IC leader providing the best products and services. For more information about Zinitix Co., Ltd, please visit http://www.Zinitix.com/eng/main/main.php

Continue ReadingZinitix BT541 Touch Screen Controller Uses Andes N968A

Andes Technology Forms New Internet of Things Community Knect.me to Provide Open-Source and Commercial IoT Solutions based on AndesCore™ processors

Knect.me Partner Solutions Enable SoC Developers to Build Highly Competitive IoT Products to Meet Narrow, Fast-Moving Product Windows

【Taiwan Hsinchu】– Andes Technology Corporation, the leading Asia-based supplier of small, low-power, high performance 32-bit embedded CPU cores, today announced knect.me, the new Internet of Things community that provides open-source and commercial solutions for connected devices based on the highly performance-efficient AndesCore processors. Knect.me community partners provide the SoC development platforms, software stacks, application development platforms, and development tools SoC developers need to build highly competitive IoT products to meet narrow, fast moving product windows.

“IoT is a diversified market with great potential. In the past year, many partners have approached Andes seeking partnership,” said Charlie Hong-Men Su, Ph.D. Andes Technology CTO and Senior Vice President of R&D. “Because we know that it takes multiple companies cooperating to fully exploit a market potential. Andes would like to contribute to the expansion of the IoT market by providing enabling resources for developers. With this motivation in mind, we created a new website knect.me. The site will connect chip vendors, partners, applications developers, and system vendors related to IoT. Knect.me will also bring together solutions for silicon IP’s, software stacks, tools, applications, and systems to help develop products that will connect to the world.”

In addition to the knect.me community, Andes is also creating the “IoT League.”  The league will showcase successful products that have been developed through the knect.me community. “We’re inviting Andes’ customers to provide information on their products that contain AndesCore IP,” said Frankwell Jyh-Ming Lin, Andes Technology President. “In return, IoT League participants will receive greater exposure and enhanced reputation in the IoT market. By showcasing a broad expanding array of applications, new prospects will be attracted to adopt Andes customers’ products and solutions.”

About Knect.me solution
The Knect SoC Development Platform solution comprises the AndesCore™, Andes platform IP, and partners’ IPs. The Knect Software Stack provides choices of open source software, and production-proven, certified and optimized software by Andes partners to fulfill a wide range of smart products and emerging applications development requirements. The Knect Application Development Platforms include both FPGA based prototyping boards and ASIC based rapid development boards. The Knect Development Tools include the AndeSight IDE Lite and the open source GNU toolchain for AndesCores. AndeSight™ Lite is a compact version of the Eclipse-based AndeSight™ IDE for free download. It comes with all major functionality up to a code size limitation of 32KB.

Availability
The knect.me community website is available immediately at http://www.knect.me, or simply knect.me. For information about joining the knect.me community or to participate in the partnership program or IoT League, contact knectme@andestech.com

Continue ReadingAndes Technology Forms New Internet of Things Community Knect.me to Provide Open-Source and Commercial IoT Solutions based on AndesCore™ processors

Andes CPU Core Small Die Area and Low Power Consumption Wins New Socket in MediaTek SoCs

Andes Technology Corporation, the leader in developing easy to integrate, scalable, and configurable CPUs and platforms, announced this month that MediaTek Inc., a leading fabless semiconductor company, has adopted the AndesCore™ N9 CPU IP in their SoCs. The AndesCore™ N9 is intended for deeply embedded applications that require optimal interrupt response time, efficient performance and compact code size, including wireless networking and sensors.

“We are thrilled that AndesCore N9 was selected for use in the MediaTek SoCs,” said Dr. Charlie Su, Chief Technical Officer and SVP of R&D at Andes. “The N9 dramatically reduces the instruction memory size and cost of the SoC through higher code density, when compared to legacy 8- or 16-bit MCUs. Despite the N9’s compact size, it still provides more than 40 percent better performance than competing 32-bit processor cores to enable functionality such as 802.11 drivers and TCP/IP protocol stack for network applications, GPIO and PWM for intelligent control, as well as UART and SPI interfaces for device communication.”

According to market analyst BI (Business Intelligence), smart home device shipments will grow faster than smart phones or other portable devices, at a compound annual rate of 67 percent for the next five years. The market research firm expects as many as 1.8 billion units to ship in 2019, including safety and security devices such as internet-connected sensors, monitors, cameras, and alarm systems and energy management components such as smart thermostats and lights. As Andes customers produce SoCs for this market opportunity, embedded processors such as the N9 will continue to see strong demand.

Continue ReadingAndes CPU Core Small Die Area and Low Power Consumption Wins New Socket in MediaTek SoCs

Andes Unleashes AndeSight™ v2.1.0 IDEs, Offering Mature Development Suites to Satisfy Diversified Requirements


【Taiwan Hsinchu】Andes Technology Corporation, the leading vendor dedicated to 32-bit CPU IPs and associated SoC platforms in Asia, recently launched AndeSight™ v2.1.0 IDE in four different editions – STD (Standard), MCU, RDS (ReDiStribution), and Lite – to satisfy diversified market and customers. Prior to this release, the entry-level AndeSight v2.0.1 MCU/RDS IDE and the high-end AndeSight v2.0.1 STD IDE have already been widely adopted in the industry due to the user-friendly, powerful and fast-time-to-market characteristics. Inheriting advantages from these predecessors, the four AndeSight v2.1.0 editions are further enhanced to address specific needs of SoC developers. The STD edition is for Linux application development or development with virtual evaluation platforms while the MCU edition is designed to align with the development flow of MCU programs. Based on the MCU version, the RDS edition allows chip vendors to provide their customers an optimal development environment containing chip- or application-specific customized components, which include new graphical user interface (GUI), sample code, SoC settings and configurations, and an utility for flexible version control. Lastly, the Lite edition is a compact, evaluation AndeSight IDE targeting software developers of IoT or wearable devices. 

AndeSight v2.1.0 editions feature intuitive and refined GUI based on Eclipse CDT 8.0 platforms and enclose BSP v4.0.0 toolchains that boost code density and performance with better efficiency. They also provide complete support for AndesCore™ processor families (including N7, S8, N8, E8, N9, N10 and N13) and feature powerful functions like LdSaG editor, EVB profiling, code coverage analysis, function code size calculation, COPILOT (COProcessor Instruction DeveLOpment EnvironmenT) support, RTOS awareness debugging, flash ISP (in-system-programming), plug-in API, and internationalization support for three languages: English, Simplified-Chinese and Japanese. With outstanding debugging capabilities and significant code optimization, AndeSight facilitates program development on hardware platforms when working with Andes ICE solutions AICE-MCU or AICE-MINI. Designed to meet diversified requirements, the easy-to-use AndeSight v2.1.0 IDEs with high-performance toolchains enable Andes customers to gain competitive advantages and accelerate time-to-market.

AndeSight v2.1.0 MCU is the edition tailored for MCU programmers. Its toolchains support the extensible E8 core as well as standard Andes cores. Based on AndeStar™ V3/V3m ISA, these toolchains allow a development environment of All-C Embedded Programming and offer fine-tuned RTOS awareness support. To give users a jump start on using Andes cores and AndeSight, this MCU edition comes with startup demos in the package. Users may also utilize the simulator or target board profiling function to identify performance bottlenecks and tune application code accordingly. This IDE edition supports CPU cores with the ACE (Andes Custom Extension™) framework, such as E8. The ACE framework helps SoC developers simplify the instruction design process. Based on ACE descriptions, COPILOT generates the corresponding extension modules to be used with Andes standard development tools, debugging tools, simulator and AndesCore RTL, rendering an exclusive development environment for the CPUs newly created by SoC developers.

Regarding to debugging tools, AndeSight v2.1.0 MCU can work with Andes low-cost, high-efficiency ICE solutions AndeShape™ AICE-MCU and AICE-MINI through two-wire Serial Debug Port interface, benefiting developers from reduced pin counts and SoC costs. The AICEs support the advanced Debug-on-Reset and Secure Access features in addition to AndesCore’s standard debugging mechanisms such as hardware breakpoint and single step execution. They provide auto frequency calibration and use OpenOCD as its management software to achieve an even faster download speed compared to the last version. They also support new AndeSight features such as EVB profiling function, exception handling and problem diagnosis.

In terms of building custom development environment, AndeSight v2.1.0 MCU provides extensive supports including chip profile editor, plug-in API, and LdSaG editor. Based on the characteristics of individual SoC, the GUI chip profile editor facilitates developers to quickly specify parameters for relevant components like project template, toolchain, memory map, flash driver and SoC registers before generating chip profiles accordingly. The flexible plug-in API allows users to develop additional but fully-integrated GUI by directly accessing AndeSight resources. The LdSaG editor is newly introduced to AndeSight. It enables users to create the much simplified linking description SaG (Scattering-and-Gathering) files with ease through a drag-and-drop interface. A SaG file is automatically converted to a GNU linker script file for use in linking by Andes linker script generator utility.

AndeSight v2.1.0 Lite is a compact version derived from AndeSight v2.1.0 MCU and can be downloaded free of charge. It includes a V3m toolchain and has a code size limitation of 32KB. Poised for evaluation or prototyping development with virtual or physical platforms of Andes low-power processors, AndeSight v2.1.0 Lite is best-suited to develop a wide range of innovative IoT and wearable devices.

AndeSight v2.1.0 RDS is the redistribution edition descended from AndeSight v2.1.0 MCU too. It is for SoC vendors to provide their customers a tailor-made environment based on their SoCs for the best development efficiency. Examples of customizable items include new GUI designed through plug-in API, flash burner, SoC register definitions, memory maps, compiler/debugger options, sample code, and documentation.

Last but not least, AndeSight v2.1.0 STD is the version offering the most comprehensive features. In addition to functions in the MCU counterpart, the STD edition includes enhanced functionalities for development environment setup, debugging and verification. With regard to program debugging, this edition extends its support to Linux application development by providing in-time debugging and attach-to-process debugging through Process View. In addition, its performance profiling covers all activities in the system and allows users to analyze the time spent on user processes, system libraries and kernel. Supporting both Windows and Linux platforms, it enables a fully integrated GUI development environment, containing software management, compiling, flash programming, debugging, and profiling, for all Andes processors.

Dr. Charlie Su, Chief Technical Officer and VP of R&D at Andes, stated, “In Andes, the launch of quality and efficient development tools is deemed just as importantly as the release of leading AndesCore embedded processor IPs. That is why we set a continuous goal to deliver easy-to-use AndeSight IDE with higher efficiency, optimized code and all-around supports for hardware, software and system. The AndeSight v2.1.0 IDEs are the outcome of numerous internal discussions and revisions incorporating customer feedbacks. Its performance boost and compelling new features like hardware profiling, code coverage and LdSaG editor not only manifest Andes’ achievements on advancing development tools but also demonstrate our continuing commitments to customers.”

For more information about AndeSight v2.1.0 IDEs, AndeShape AICE-MCU or AICE-MINI, please refer to www.andestech.com or contact sales@andestech.com

Continue ReadingAndes Unleashes AndeSight™ v2.1.0 IDEs, Offering Mature Development Suites to Satisfy Diversified Requirements

Andes and eMemory Announce New IC Security Solutions For IoT Security Applications

【Hsinchu, Taiwan.】 – The rapid development of Internet-of-Things (IoT) offers advanced interconnection between various devices and systems. As consumers place greater concern on data security and protection mechanism, the demands for related IC security solutions increase simultaneously. Targeting the market demands, eMemory Technology, the logic non-volatile memory (Logic NVM) and silicon intellectual property (Silicon IP) industry leader, partnered with Andes Technology Corporation, the first developer of original 32-bit microprocessor IP and system IC design in Asia, to launch new IC security solutions for IoT security applications market.

The AndesCore™ S801 secure 32-bit processor elevates the safety of data transfer and storage in embedded applications. Applying AndesCore™ S801 in System-on-Chip (SOC) designs along with eMemory’s one-time programmable (OTP) silicon IPs for security key storage in IoT products, the data security can be greatly enhanced at the minimum cost. Therefore, the new security MCU solutions find the perfect balance between information security and product cost, which can greatly benefit customers to exploit the boundless business opportunities offered by IoT.

To take the lead in the IoT market, the data security of IC hardware and firmware is crucial. Targeting the market potential, Andes launches the AndesCore™ S8 series products which equip with compact 3-stage pipeline and protected command set for diverse password and anti-tampering applications. Apart from comprehensive protocols for access control, the AndesCore™ S801 also features an energy-saving core and a secure memory protection unit (Secure MPU), offering hardware protection for program codes and data to prevent side-channel attacks.

The AndesCore™ S801 is fully conforming to the latest SoC designs. It can facilitate customers’ product development and certification approval process, as well as reduce time-to-market; making it the best choice for secure products which emphasize lightweight, compact size, and low-power consumption designs. AndesCore™ S801 can be widely applied in various applications to provide security mechanism and added-value, such as NFC, smart cards, bank cards, health cards, e-passports, smart meters, sensor hubs, smart locks, smart home, and the wearables.

Unlike conventional ICs with metal-fuse or poly-fuse based architectures, eMemory’s Logic NVM IPs use floating-gate and anti-fuse structures to prevent reverse-engineering, hence effectively protect data from detection and interpolation to enhance information security. The advanced security level of eMemory’s NeoFuse silicon IP has been recognized by the Conditional Access (CA) certification. Moreover, eMemory OTP silicon IPs  offer 125℃/10 years industry-grade high-temperature data retention ability, which are ideal for products with strict operational conditions and performance demands.

eMemory’s Logic NVM IPs are fully compatible with generic CMOS processes without additional mask layers. They have been extensively deployed in 0.5um~16nm process platforms at worldwide foundries; which offer customers not only a wide range of platform choices for product planning and validation, but also high flexibility of production capacity to maximize manufacturing competitiveness.

The strategic alliance of Andes and eMemory will provide customers competitive advantages to exploit opportunities in the growing IoT market, and further expand application ranges into mobile payments, smart home, automotive electronics, and cloud data centers. Combining the low-cost, low-power consumption, and high-security benefits of AndesCore™ S801 32-bit processor with eMemory OTP silicon IPs’ cost-effective, high-reliability, high-temperature data retention features, and diverse platforms availabilities; both parties can assist their partners to develop high-end security products to take the lead in the global market.

About eMemory
eMemory (Stock Code: 3529) is a global leader in logic process embedded non-volatile memory (eNVM) silicon IP. Since established in 2000, eMemory has been devoted to research and development of innovative technologies, offering the industry’s most comprehensive platforms of patented eNVM IP solutions include NeoBit (OTP silicon IP), NeoFuse (anti-fuse OTP silicon IP), NeoMTP (1,000+ times programmable silicon IP), NeoFlash (10,000+ times programmable silicon IP), and NeoEE (100,000+ times programmable silicon IP) to semiconductor foundries, integrated devices manufacturers (IDMs) and fabless design houses worldwide. eMemory’s eNVM silicon IPs support a wide range of applications include trimming, function selection, code storage, parameter setting, encryption, and identification setting. The company has the world’s largest NVM engineering team and prides itself on providing partners a full-service solution that sees the integration of eMemory eNVM IP from initial design stages through fabrication. For more information about eMemory, please visit www.ememory.com.tw

Press Contact
eMemory Technology Inc.
Public Relations Department
Michelle Wang
Phone: +886-3-5601168 #1121
Email: michelle@eMemory.com.tw

 

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