Andes Exhibits at TSMC 2014 NA Technology Symposium Ecosystem Pavilion

Andes Technology exhibited at the TSMC 2014 NA Technology Symposium Ecosystem Pavilion, San Jose McEnery Convention Center, California, on April 22. Participating with other TSMC OIP (Open Innovation Platform) ecosystem member companies, Andes as an IP partner introduced its high performance, low power 32-bit processor core families with SoC development environment to attendees and showcased AndesCore™-embedded applications which have been in mass production. In the exhibition, booth visitors were impressed with Andes’ competitive CPU IPs and robust platform solutions while exchanging information with Andes US staff. Andes also demonstrated in the event that it’s ready to get deeper and broader involvement in the design ecosystem with its most advanced CPU IP technology.
 

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Andes Technology Launched AndeStar™ V3

 a New-Generation Smart Low-Power 16-/32-bit Mixable Instruction Set Architecture (ISA), to Reduce IC Cost, Improve Efficiency, Facilitate Development and Shorten Time-to-Market 

【Taiwan HsinChu】For years, Andes Technology has been dedicated to developing CPUs and platforms that deliver easy integration, scalability, and design flexibility. To cater to demands of IC design companies and OEMs, it also offers comprehensive product lines and feature-rich development tools. Recently in its 7th Andes-Embedded™ Forum, Andes Technology announced the launch of AndeStar™ V3, a new-generation, smart, low-power Instruction Set Architecture (ISA). AndeStar™ V3 is 16-/32-bit mixable ISA and backward-compatible to V2 ISA. It minimizes executable code size to allow customers to adopt smaller-sized memory to reduce IC cost or put more features in the same-sized memory. In terms of MCU benchmarks, AndeStar™ V3 demonstrates executable code size reduction of over 20% on average when the size of the V3 code is compared to that of the preceding V2 code. With the introduction of All-C Embedded Programming development environment, AndeStar™ V3 enhances the performance of interrupt handlers and improves debugging capabilities, thereby significantly shortening product development cycle and time-to-market for customers.

The applications of AndeStar™ V3 are extensive, including networking, DTV, Digital Home, DSC, DVD, game consoles, PC peripherals, storage, smart meters, industrial control, automobiles, medical devices, and various communication protocols such as Bluetooth and WiFi. AndeStar™ V3’s features and functionalities serve to raise the competitiveness of these product applications in the global market.  

Dr. Chuan-hua Chang, Director of Architecture Division at Andes, stated, “V3-based CPUs can run V2’s executable code as AndeStar™ V3 is backward-compatible. After upgrading their CPU cores to V3-based CPUs, existing V2-based CPU customers do not have to modify or recompile their programs in a hurry. However, they can benefit fully from the features of V3 ISA by recompiling their programs. The V3 program development toolchain will use special instructions to reduce repeated instructions, replace frequently-used instruction sequences with fewer instructions, and use shorter instructions to handle common tasks of functions. These features all bring effective boosts to code density.”
Dr. Chuan-hua Chang further explained, “AndeStar™ V3 offers compiler support for hardware architecture. That is, it provides a development environment of All-C Embedded Programming for developers to write all their code in C and save the trouble of using assembly language. As to interrupt service routines, AndeStar™ V3 adopts priority-based preemptive interrupt scheme. CPU will handle an interrupt request with the highest priority first, thus speeding up the handling of higher priority interrupts and increasing overall efficiency. Moreover, AndeStar™ V3 also improves debugging capabilities, enabling early discovery of problems that are not very obvious. – With all these features, AndeStar™ V3 not only accelerates time-to-market but also greatly reduces development time, revision, and maintenance overhead.”

Please contact sales@andestech.com for more information about AndeStar™ V3, the new-generation smart low-power backward-compatible 16-/32-bit mixable Instruction Set Architecture.

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Andes Technology Launched AndesCore™ SN801, the New Generation Processor Core with Security Features.

With High Power-Efficiency and Side Channel Attack Prevention, SN801 Becomes the Best Choice for SoC Developers when Designing Lightweight and Low-power Secure Products.
 

【Taiwan HsinChu】For new-generation SoC design, delivering 32-bit features and performance along with 8/16-bit cost is a must if one wants to stand out in a competitive market. To meet these requirements, Andes Technology launched the latest-generation AndesCore™ SN801, a 32-bit CPU with advanced security features, in its recent 7th Andes-Embedded™ Forum. SN801 is based on the energy-efficient N801 processor core and designed with secure MPU (Memory Protection Unit). It not only adopts a comprehensive protocol to manage privilege levels but also provides hardware mechanisms for code and data protection. Effectively preventing side channel attacks, AndesCore™ SN801 processor core is the best choice for SoC developers to design lightweight and low-power secure products.

AndesCore™ SN8 series combines streamlined 3-stage pipeline with protective instruction set architecture. With its complete and robust architecture, SN801 enables customers to assign security levels by setting passwords or implement tamper-proof mechanisms according to application needs. The applications of SN801 cover from emerging NFC, bank cards, medical insurance cards, memory cards to e-passports and more. By migrating to SN801 that significantly surpasses legacy 8/16-bit processors, IC design companies can hammer out low-cost, low-power, highly secure and competitive products to address ever-renewing and fast-growing applications.

Dr. Charlie Su, Chief Technical Officer and VP of R&D at Andes, states, “According to a market research report, the global shipments of smart cards are expected to reach around 8.5 billion units by 2013. Specifically targeting applications pertaining to smart cards, AndesCore™ SN801 accelerates the associated SoC design and development, reduces the time for product certification and speeds the entry to market, thereby benefiting customers to vie for share of the ten-billion-unit smart card market. AndesCore™ SN801 fully caters to the demand of new generation SoC design with its 32-bit features and 8/16-bit cost advantage, making it the optimal choice for SoC developers when designing lightweight and low-power secure products.”    For more information about the embedded AndesCore™ SN8 series, please refer to www.andestech.com or contact sales@andestech.com

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Andes Leads The Industry by Reducing Power Consumption for New Embedded Devices New Lower-Power Processor Solutions for Wearable Computing, IOT and other Power-Critical Applications

【Santa Clara, CA, October 2, 2013】 – Andes Technology (www.andestech.com), Asia’s leading supplier of licensable processor cores, today disclosed plans for a new class of ultra-low power processor core solutions.  These products will incorporate a new technology called FlashFetch™ as well as other energy reducing innovations.  Collectively, these new capabilities are designed to meet the most demanding, power-sensitive requirements for applications such as Wearable Computing devices, IoT (Internet of Things) and other flash-memory based requirements.  Building upon Andes’ successful line of performance-efficient IP cores, already in hundreds of millions of products, the company is breaking new ground by further reducing energy consumption and extending battery life to enable a new class of devices.

Speaking from TSMC’s Open Innovation Platform(OIP) ecosystem conference, Andes’ President, Frankwell Lin, explained: “Reducing energy consumption is a global need and we are committed to help that through innovations in performance-efficiency.  These new products enable our customers to rebalance performance and power consumption, resulting in SOCs that consume less energy to accomplish their work.  This helps extend battery life for the next generation of embedded devices – like the new Wearable Computing products that are starting to emerge.”  Andes is demonstrating their entire product line at their booth at the OIP conference.

Andes new low power solutions have impact beyond the processor cores.  The techniques used allow lower speed memories to be used, saving power without sacrificing performance and also enable the creation of off-core program buffers.  Moreover, modeling application performance of is simplified with the AndesSight™ development environment.  This allows customers to experiment with alternate hardware approaches to optimize power, performance and size for their specific software.

“As the new class of SoC solutions for IoT applications becomes better defined, one trend that is emerging is the need for very low power consumption and high power efficiency in the silicon,” said Rich Wawrzyniak, Sr. market Analyst at Semico Research. “Approaches and products that allow designers to realize good performance while delivering power efficiency will be well-received in the market and enjoy a large degree of success.” Wawrzyniak went on to say, “the research Semico is doing today on IoT applications shows the potential for very large unit volumes in the near future to support IoT implementations in both consumer and commercial environments. Good solutions in one area have the potential of being adopted in other areas of the market and the Andes Technology use of the FlashFetch technology can impact silicon solutions aimed at these other market segments. This design solution can have a synergistic effect on Andes’ growth into these newer market segments.”

These new low power solutions featuring FlashFetch, COPILOT, PowerBrake and other new techniques will be discussed at the upcoming Linley Tech Processor Conference on October 16th and 17th at Hyatt Regency, Santa Clara. 

For more information about the AndesCore™ N7 Series, FlashFetch or any of our other low-power, high-performance IP cores and subsystems, please refer to www.andestech.com or contact us at america@andestech.com

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Andes Embedded Processor Symposium 2013 Held in Korea

Co-organized by Andes and KIPEX, Andes Embedded Processor Symposium 2013 was held on Sep 12, 2013 at EL Tower, Seoul, Korea. Specially designed for embedded SoC designers and ASIC design service companies, speeches focused on Andes high performance, low power 32-bit processors and the associated SoC development platforms. Attendees were introduced to new-generation SoC solutions that meet rapidly-growing demands on better scalability, flexibility, performance, cost and power saving.

In the symposium, Andes Sales VP presented three major trends of device creation, the evolution of embedded CPUs and the MCU market analysis; Andes FAE Director introduced Andes advantages in hardware for MCU applications and Linux applications; Andes Sr. Technical Manger introduced Andes proprietary instruction set architecture AndeStar™, Andes software development environment AndeSight™ and complier optimization.

The symposium will be held periodically in the future. Through the event, Andes plans to bring the first hand technology development to the Korean industry and enhance interaction with customers there.

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Andes Launches AndeSight™ v2.0.0 STD Edition, Offering SoC Developers a Sophisticated Development Suite to Ｍeet Diverse Requirement

【Taiwan HsinChu】 Andes Technology, the dedicated vendor of 32-bit CPU IP and associated SoC platforms, launches the AndeSight v2.0.0 STD Development Suite tailored for middle- and high-end market after the rollout of its MCU version for low-end market. AndeSight v2.0.0 STD is characterized by its brand new GUI layout based on Eclipse CDT 8.0 and customization features Chip Profile, Flash ISP and Plugin API with excellent integrity. In addition to the existing AndesCore™ processor cores, AndeSight v2.0.0 STD extends its supports to the newest member, N1337, and cooperates with the Andes ICE solutions, AndeShape™ AICE and AICE-MCU. With these features, AndeSight v2.0.0 STD has become a sophisticated development tool that can catch up with the future trend and meet diverse requirements. 

AndeSight v2.0.0 STD not only includes functions in the MCU version but also enhances its functionalities for setting up the development environment, debugging and verification. Integrating with Andes ESL Integrated Virtual Environment AndESLive™, AndeSight v2.0.0 STD comes with virtual evaluation platform Simulator and graphical interface SoC Builder that enables the construction of virtual SoCs. In terms of debugging, it provides two configurations specific for Linux target environment – Linux Application debugging and Attach to Process debugging. 

AndeSight v2.0.0 STD also offers various functions to customize development environment, including Chip Profile, Flash Burner and Plugin API. Chip Profile contains project templates for specific targets, preventing developers from repetitive configuration for the same targets. As to Flash Burner, users can modify the sample Flash Driver to meet their own flash type and perform pertinent flash programming through the built-in Flash ISP graphical interface. Plugin API allows users to utilize the resources of AndeSight with their own plugin programs. The graphical interface Chip Profile Editor facilitates developers to quickly configure Chip Profile components for individual SoCs. A Chip Profile can be generated by simply configuring the parameters of Chip Profile components, such as project template, Flash Driver, SoC Registers, and Memory Map.

The toolchains of AndeSight v2.0.0 STD support existing CPU N7, N8, SN8, N9, N10 and also N13, the newest member of AndesCore family. Supported by AndeStar™ V3/V3m ISA, the toolchains enable a development environment of All-C Embedded Programming. Programmers can produce high quality code efficiently by writing all their code in C and save the trouble of using assembly language. On the side of RTOS support, AndeSight v2.0.0 STD provides RTOS Awareness feature for μC/OS-II and FreeRTOS, rendering developers visualized high-level debugging for RTOS applications. 

With regard to the debugging solutions, AndeSight v2.0.0 STD can work with both AndeShape AICE and AICE-MCU. The former has been enhanced to deliver better functionality and efficiency; the later supports two-wire JTAG interface so that users can be benefited from reduced pin counts and SoC cost. AndeShape AICE-MCU supports the Debug-on-Reset and Secure Access features in addition to AndesCore’s standard debugging mechanisms such as hardware breakpoint and step-over. It also provides auto frequency calibration and effective download speed, offering customers a low cost niche while maintaining high compatibility with development environment.  

Based on AndeSight v2.0.0 MCU, the newly-launched STD version has a significant upgrade on efficiency and stability. It allows SoC engineers to develop programs on virtual SoC platforms and perform verification on real boards. It also provides advanced debugging utilities to ease the development process and various startup demo programs to get users acquainted with hardware/software environment in less time. 

Dr. Charlie Su, Chief Technical Officer and VP of R&D at Andes, states, “To Andes, introducing high quality and efficient development tools are just as important as launching leading embedded CPU IP AndesCores. We expect AndeSight to be easy-to-use, deliver higher efficiency with optimized code and provide extensive supports for hardware, software and system. The new features of AndeSight v2.0.0 STD are derived from customers’ feedbacks, numerous internal discussion and revisions. Its performance, new functionalities and customization features Chip Profile Editor and Plugin API demonstrate Andes’ continuous efforts on software enhancement and fulfill our commitments to the customers. We look forward to seeing our customer Seize Today’s Dreams and Shape Tomorrow’s Devices with AndeSight v2.0.0 STD.”

For more information about AndeSight v2.0.0 STD Edition and AndeShape AICE-MCU, please refer to www.andestech.com or contact sales@andestech.com

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Andes Launches the First Andes Certified Engineer Program

Students Flock to Register for Understanding Taiwan-based Development Platforms and Developing Professional Skills

【Taiwan HsinChu】The first Andes Certified Engineer (ACE™) Program was launched successfully in December 2012 in Kun San University, southern Taiwan, and Chien Hsin University of Science and Technology, northern Taiwan. The exam-based certification included two levels, advanced and intermediate, and had 96% attendance among 138 registrants. 
Andes Technology, the dedicated vendor of 32-bit CPU IPs and associated SoC platforms, introduces the ACE Program to make up the gap between universities and industry. The ACE program itself also adds values to Andes and boosts Andes’ corporate image when the Taiwan-based company goes international. Focusing on CPUs and embedded systems, the ACE Program facilitates the promotion of Taiwan-based developed products and the industry-academia cooperation. It also benefits students by getting them involved with the development process of SoC platforms, familiar with R&D environment in Taiwan, and ready for technology jobs. In the end, the ACE Program is expected to bring more advantages in promoting and nurturing the local CPU IPs.

Dr. Jhih-Syue Jhou, the supervisor of the first ACE Program and an associate professor in Department of Information Engineering, Kun San University, stated, “It’s my honor to organize the ACE exam in southern Taiwan and introduce the Taiwan-based embedded SoCs to students. I would like to express my respect to Andes Technology for their contributions on embedded system industry and related education in Taiwan. The program was launched successfully thanks to the support from the head, Prof. Benjamin Tseng, the staff and students in my department. Without their helps, it wouldn’t be easy to host an exam with 105 registrants.” 

Prof. Jhou further noted, “The industry needs qualified engineers and students need a certification to demonstrate their expertise. That’s why we hosted the exam to bridge the gap between the industry and students. Through the promotion by my department, 95% of students taking related courses had registered for the exam. The attendance clearly reflects the industry trend and the market demand. Kun San University and Department of Information Engineering would like to host the exam continuously with our full support. We also expect to set up a test/certification center and a training center in our department; the former allows more exam sessions for engineers in related fields to participate while the latter can do more promotion for Taiwan-based SoCs.”

The President of Andes Technology, Frankwell Lin, said, “Via the ACE Program, students can learn more about embedded systems and hardware/software co-design, thereby gaining the edge in job application. The ACE Program is devised as a training for corporate customers. University or graduate school students taking this exam can be exposed to industry-level embedded system development. Moreover, since a great part of the ACE Program is derived from frequently-asked questions of Andes customers, students can consider it as a rehearsal chance for job interview. We are glad that the first ACE Program has successfully launched and grateful for the supports from organizers, supervisors and test administrators in both venues. We also thank for the advices of Embedded Software Consortium, Education of Ministry. With the successful debut of the ACE Program, we will keep the event going and schedule it every half year.” 
  
For more information about the Andes Certified Engineer (ACE™) Program, please refer to www.andestech.com or contact ace@andestech.com

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The 8th Andes-Embedded™ Forum (AEF) Invites You to Seize Today’s Changing Moment and Create Tomorrow’s Groundbreaking Devices

Andes Technology Launches its Compact Processor Core “Hummingbird” That Delivers Ultra Low Power Consumption, Adequate Performance with Reduced Cost

【Taiwan HsinChu】The 8th Andes-Embedded Forum (AEF) has successfully taken place on April 18, in Hsinchu, Taiwan. Bearing the motto “Driving Innovations” in mind to self-motivate and service customers, Andes Technology has been providing core technology, SoC key components and development platforms for years. With the same mindset, the AEF in 2013 had a theme to assist customers to “Seize Today’s Changing Moment and Create Tomorrow’s Groundbreaking Devices” with Andes processor-based solution and professional technology support. In the event, Andes Technology unveiled its compact 32-bit processor series “Hummingbird,” the achievement of Andes’ 8-year research that delivers ultra power-efficiency and adequate performance while reducing more die size and unit cost. Many of Andes partners were also invited to give product demonstrations.

In an era of pursuing smart and green product designs, computing in ultra low power consumption are extremely important. Thus, the 8th AEF aimed to provide customers with solutions of low power consumption and operation acceleration in hopes of making them meet their targets earlier. Attendants to this event got a thorough understanding through AEF’s eight sessions of different topics and ten booths that showcased various Andes applications. The theme of the AEF this year, “Seize Today’s Changing Moment and Create Tomorrow’s Groundbreaking Devices,” responded to the two main requirements for today’s applications – power consumption and performance. Andes Technology with its CPU solutions looks forward to giving all SoC engineers a big hand to launch target-met SoCs and shorten the time to market. The Andes-embedded SoCs in turn are believed to facilitate the design of next-generation eye-catching devices for system engineers.

Jyh-Ming Frankwell Lin, President of Andes Technology Corporation, stated, “According to an IDC research report, the uptake of smart phones and tablets continues to surge these years. In 2013, the shipment of smart phones is projected to grow 13% while that of tablets is 44%, showing that mobile devices still play a prominent role in the market. This trend stimulates the rise of new applications and brings business opportunities to related industries. Knowing that it’s a must to enter the mobile device market, Andes Technology has acted aggressively to gain its share in fields like portable devices, IoT (Internet of Things), touch devices, networking, wireless communication, MCU and multimedia applications these past few years. When there is a need to adopt SoC(s) in your product, there is a chance for Andes Technology to partner with you. Providing core technology and development platform, Andes has worked closely with our customers to smooth the development process and to reduce their time-to-market. That’s how the theme of AEF this year, “Seize Today’s Changing Moment and Create Tomorrow’s Groundbreaking Devices,” came from. We believe that AEF attendants have all been benefited from the mutual exchange of experiences and information about different applications in the event.”

Lin further expressed, “We keep offering best support and service expecting that SoC companies consider Andes when they develop their products. We also constantly launch products to answer to customers’ needs. The processor series ‘Hummingbird’ introduced in the AEF is tailored for embedded controllers that require ultra low energy consumption, especially for those that require months, or even longer, of battery life. As lightweight and vigorous as hummingbirds, the compact processor series ‘Hummingbird’ delivers ultra energy-efficiency while charging pretty low unit cost and power. Its applications include sensor-based applications, IoT, medical devices, MCUs, mobile phones, smart phones, tablets, wireless communication, wireless connection, Wi-Fi, Bluetooth, GPS, Navigation System, sensor network, sensor fusion, and all sorts of hand-held devices. ‘Hummingbird’ outperforms its competitors with both ultra low power consumption and better performance; it enables the completion of a task faster using minimum power and enters the stand-by mode immediately to wait for the next task. Thus, ‘Hummingbird’ is by all means the most energy-efficient processor core in the market.”

For more information about the 8th Andes-Embedded Forum (AEF) and AndesCore, Andes 32-bit processor core IP, please refer towww.andestech.comor contact sales@andestech.com

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Andes Offers Training Courses to Universities in Beijing

From May 13 to 22, Andes offered a series of training courses to universities in Beijing of China including Peking University, Beijing Institute of Technology, and Beijing Jiaotong University. These courses presented Andes’ high-performance, low-power 32-bit processors AndesCore™ with their applications in embedded systems. They also introduced the corresponding development environments of Andes cores and provided hands-on trainings in the use of Andes’ IDE, AndeSight™. Students taking these courses not only acquired theoretical knowledge and practical skills but also got inspired in the follow-up open discussion sessions.

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