Read more about the article Andes Technology and MetaSilicon Collaborate to Build the World’s First Automotive-Grade CMOS Image Sensor Product Using RISC-V IP SoC

Andes Technology and MetaSilicon Collaborate to Build the World’s First Automotive-Grade CMOS Image Sensor Product Using RISC-V IP SoC

Feb. 22, 2024 — RISC-V IP vendor Andes Technology and edge computing chip provider MetaSilicon jointly announced that the MetaSilicon MAT Series is the world’s first automotive-grade CMOS image sensor series using RISC-V IP SoC, using Andes’ AndesCore™ N25F-SE processor. They are designed in accordance with the ISO26262 functional safety standard to achieve ASIL-B level and follow the AEC-Q100 Grade 2 to achieve a high level of safety and reliability. And by using technologies such as HDR, advanced imaging can be achieved in a simple, economical, and efficient system. They not only address the effects of high dynamic range, high sensitivity, and high color reproduction, but also meet the application requirements of ADAS decision-making.

The N25F-SE from Andes Technology is a 32-bit RISC-V CPU core that can support the standard IMACFD instruction set, which includes an efficient integer instruction set and a single/double precision floating point operation instruction set. The N25F-SE’s high-efficiency five-stage pipeline achieves a good balance between high operating frequency and a streamlined design. It also has rich configurable options and flexible interface configuration, which greatly simplify the SoC development. In addition, the N25F-SE has obtained the ISO 26262 ASIL-B full compliance certification, which enables the image sensor chip to meet the vehicle-level safety requirement. For the development of MetaSilicon’s automotive-grade chips, the N25F-SE and its safety package provide a good fit CPU solution and together with Andes’ technical support shorten the chip development time significantly.

MetaSilicon has first-class innovative R&D capabilities and has developed several cutting-edge technologies including LOFIC (Lateral Overflow Integration Capacitor) + DCG (Dual Conversion Gain) HDR (High-Dynamic Range), which meet the high-quality image requirements for smart car vision applications. The MAT Series 1MP CMOS image sensor chip has low power consumption and high dynamic range (HDR) characteristics. Its effective image resolution is 1280 H * 960 V, and it can support high dynamic range image output up to 60fps @120dB. The other MAT Series 3MP CIS has multiple capabilities such as low power consumption, ultra-high dynamic range (HDR), on-chip ISP, LFM, etc. Its effective image resolution is 1920 H * 1536 V, and can support up to 60fps frame rate, and the dynamic range can reach the industry-leading 140dB+. These chips can provide reliable high-quality image information for intelligent automotive applications.

“The N25F-SE provides a safety package, which includes a safety manual, safety analysis report and a development interface outline. The N25F-SE and its safety package are effective, high-performance and flexible automotive solutions. They can significantly reduce the time required to design automotive grade SoCs and to comply with the ISO 26262 standard,” said Dr. Charlie Su, President and CTO of Andes Technology. “We are very pleased that N25F-SE’s IP and safety package efficiently support MetaSilicon shorten the development time for its two automotive-grade chips. We also look forward to more cooperation between the two companies in the future to create more innovative products.”

Jianhua Zheng, CTO of MetaSilicon said, “Among the various sensors used in automotive ADAS applications, visual image processing is particularly important. Once the image is not accurate and timely enough, it will directly lead to errors in the judgment of the back-end algorithm, so HDR performance requirements are extremely high. MetaSilicon’s LOFIC+DCG HDR technology can achieve an ultra-high dynamic range of 140dB+ to meet practical application needs in the automotive ADAS field. We are honored to work closely with Andes Technology on two high-performance chips, using the world’s first ISO 26262 certified RISC-V core N25F-SE that meets the functional safety standards. As a result, we can shorten the product development time and achieve functional safety goals.”

About Andes Technology

Eighteen years in business and a Founding Premier member of RISC-V International, Andes is a publicly-listed company (TWSE: 6533; SIN: US03420C2089; ISIN: US03420C1099) and a leading supplier of high-performance/low-power 32/64-bit embedded processor IP solutions, and the driving force in taking RISC-V mainstream. Its V5 RISC-V CPU families range from tiny 32-bit cores to advanced 64-bit Out-of-Order processors with DSP, FPU, Vector, Linux, superscalar, automotive and/or multi/many-core capabilities. By the end of 2023, the cumulative volume of Andes-Embedded™ SoCs has surpassed 14 billion. For more information, please visit https://www.andestech.com. Follow Andes on LinkedIn, Twitter, Bilibili and YouTube!

About MetaSilicon

MetaSilicon was founded in 2021. Relying on its first-class innovative research and development capabilities and the pursuit of excellence in craftsmanship, it has quickly laid out the dual industry “tracks” of automobiles and mobile phones in just 2 years. MetaSilicon’s automotive products cover electronic rearview mirrors, 360-degree surrounding imaging, advanced driver assistance system (ADAS) and other applications. With the self-developed ultra-low noise and power read-out circuits, and unique MetaHDR high dynamic range technologies, image sensors are featured by low power consumption, high sensitivity, high dynamics, and high frame rate, enabling high-end automotive applications. For more information about MetaSilicon, please refer to the official website http://www.mtsilicon.com/ .

 

Continue ReadingAndes Technology and MetaSilicon Collaborate to Build the World’s First Automotive-Grade CMOS Image Sensor Product Using RISC-V IP SoC
Read more about the article Andes Technology and Spacetouch Collaborate to Unveil High-Tech Edge-Side AI Audio Processor Featuring the Powerful RISC-V AndesCore™ D25F

Andes Technology and Spacetouch Collaborate to Unveil High-Tech Edge-Side AI Audio Processor Featuring the Powerful RISC-V AndesCore™ D25F

January 09, 2024–Andes Technology (TWSE: 6533), a leading supplier of 32/64-bit, high-performance and low-power RISC-V processor cores and a Founding Premier member of the RISC-V International, and Spacetouch Technology, a high-tech enterprise specializing in smart home, traditional home appliances, and consumer electronics, today jointly announced AndesCore™ D25F has been adopted by the SPV60 series as the edge-side audio processor, a perfect integration of traditional and intelligent audio, and introducing a new generation of on-device AI audio processors.

Andes Technology’s D25F processor, based on the AndeStar™ V5 architecture, is a 32-bit RISC-V CPU IP core equipped with P-extension (DSP/SIMD extension, draft version). Combined with the RISC-V DSP/SIMD ISA compiler, DSP library and emulator, alongside the highly optimized AndeSoft™ NN Library, customers can efficiently accelerate AI application computing. In addition, the D25F has many optional features, such as instruction and data cache, low latency local memory, and ECC for memory protection. The D25F can be configured as an AXI 64-bit or AHB 64/32-bit bus interface, and there is also a port that can access local memory directly from the outside. It can also be configured with a Platform Level Interrupt Controller (PLIC) that supports more than 1,000 interrupt sources for rapid interrupt response, prioritization, and preemption. Furthermore, the Andes Custom Extension™ (ACE) provides additional flexibility through customized special-purpose instructions. Integrated with such rich features and configuration options, the D25F provides outstanding efficiency and industry-leading performance and is the first and perhaps the most popular DSP-enabled RISC-V core in the embedded controller market.

At the same time, the new generation of SPV60 series edge-side AI audio processor chips launched by Spacetouch adopts CPU + NPU + uDSP heterogeneous multi-core architecture, combining different types of processors together to efficiently handle various tasks, especially in the field of audio processing. The design of this heterogeneous multi-core architecture presents a significant improvement for AI audio processor chips. The SPV60 series of on-device AI audio processors integrate the Andes D25F core and Spacetouch’s newly developed uDSP and AI NPU (Neural Network Processor). Among them, the D25F CPU has a maximum frequency higher than 400MHz and can handle general-purpose computing tasks. The NPU’s computing power reaches 100GOPs and is specially optimized for neural network computing. The uDSP core focuses on digital signal processing that makes special parallel acceleration according to known requirements and algorithm accumulation. The combination of these features enables better performance and efficiency in audio processing. The chip also has a high-performance audio AD (Analog to Digital) converter with a dynamic range of more than 105dB and THD+N less than -95dB; and a DA (Digital to Analog) converter with a dynamic range of more than 105dB and THD+N less than -90dB. It also has a 0V direct-drive headphone amplifier module with semi-professional performance. The chip comes with rich USB2.0, SD, SPI, UART, I2C, I2S and other peripheral interfaces, and supports AI noise reduction, AI echo cancellation, AI acoustic noise suppression, speech recognition and other algorithms. Spacetouch’s edge-side AI audio processor chips focus not only on excellent performance, but also on low power consumption. This is critical for area sensitive use cases for embedded systems and mobile devices, as they can deliver high performance while extending the battery life of the devices. Spacetouch provides professional development support including tools and reference designs, so that the SPV60 series chips can be widely deployed in intelligent voice, smart headphones, professional audio and other related fields. The chips have already entered the mass production stage.

“With the longstanding cooperation between Spacetouch and Andes Technology, our SoCs are equipped with AndesCore™ processors that offer powerful performance with multiple optional features to us.” Hu Yingzhe, CEO of Spacetouch, remarked. “The combination of the D25F RISC-V processor and Spacetouch’s heterogeneous multi-core AI audio processor IC brings more innovation and possibilities to the fields of audio processing, embedded systems and mobile devices. With the processor IP and technical support provided by Andes Technology, the two companies have a good basis to form more successful cooperation in the future. “

“Andes’ D25F with DSP/SIMD extensions offers efficient performance and flexible configurations, making it an ideal choice for high-performance embedded controllers.” Andes Technology Chairman and CEO, Frankwell Lin said. “We are very excited that Spacetouch launched this new generation edge-side AI audio processor chips in collaboration with Andes. They continue to work with us to develop successful products, while also providing helpful feedback on our processors and development tools. We look forward to Spacetouch delivering more AndesCore™ embedded products and competitive solutions to the market in the fields of smart home, traditional home appliances, and consumer electronics.”

About Andes Webinar

[Jan. 25, 2024] Join us for an engaging webinar as we delve into the boundless possibilities of RISC-V architecture with a focus on the comprehensive Total Solutions offered by the Andes Series. Explore how these cutting-edge RISC-V CPU cores are reshaping the landscape of computing, powering innovations across diverse applications such as automotive and AI. Our experts will guide you through the features, advantages, and real-world applications of the Andes Processor Series, showcasing its ability to unlock the full potential of RISC-V technology. Whether you’re in the automotive industry or the AI sector, this webinar is your gateway to understanding how Andes Series Total Solutions can elevate your projects to new heights.

Register now: https://www.linkedin.com/feed/update/urn:li:activity:7145696481008623617

About Spacetouch Technology

Spacetouch Technology, a leading high-tech enterprise in Guangdong, China, specializes in MCU+ intelligent perception and algorithms. With numerous patents, it offers comprehensive solutions in smart home, traditional appliances, and consumer electronics. In 2021, the SPT513 series gained traction, entering supply chains of top brands like Xiaomi, Honor, Walmart, and more, accumulating millions in shipments. Visit www.spacetouch.co for details.

About Andes Technology

As a Founding Premier member of RISC-V International, Andes is a publicly-listed company (TWSE: 6533; SIN: US03420C2089; ISIN: US03420C1099) and a leading supplier of high-performance/low-power 32/64-bit embedded processor IP solutions, and the driving force in taking RISC-V mainstream. Its V5 RISC-V CPU families range from tiny 32-bit cores to advanced 64-bit Out-of-Order processors with DSP, FPU, Vector, Linux, superscalar, automotive and/or multi/many-core capabilities. By the end of 2022, the cumulative volume of Andes-Embedded™ SoCs has surpassed 12 billion. For more information, please visit https://www.andestech.com. Follow Andes on LinkedIn, Twitter, Bilibili and YouTube!

Continue ReadingAndes Technology and Spacetouch Collaborate to Unveil High-Tech Edge-Side AI Audio Processor Featuring the Powerful RISC-V AndesCore™ D25F
Read more about the article Andes Announces General Availability of the New RISC-V Out-Of-Order Superscalar Multicore Processor, the AndesCore™ AX65

Andes Announces General Availability of the New RISC-V Out-Of-Order Superscalar Multicore Processor, the AndesCore™ AX65

Hsinchu, Taiwan – January 4, 2024  – Andes Technology, a leading supplier of high efficiency, low-power 32/64-bit RISC-V processor cores and Founding Premier member of RISC-V International, today proudly announces general availability of the high-performance AndesCore™ AX65 out-of-order superscalar multicore processor IP. The AX65 is the first of the high-performance out-of-order AX60 series. Equipped with 13-stage pipeline, 4-wide decode, 8-wide out-of-order execution, AX65 targets the Linux application processor sockets of computing, networking, and high-end controllers. It also received “Best IP/Processor of the Year” Award from EE Times Asia last December.

Andes has been very successful on the embedded controllers and high-performance AI vector processors. As RISC-V ecosystem for Linux is getting matured, the demand for high-performance RISC-V processors for general-purpose applications rises. Andes takes this opportunity to introduce the AX65 to complete its comprehensive CPU lineup, spanning from low-power embedded solutions to high-end Out-of-Order processors. Customers who develop complex SoC can now use AX65 as the primary Linux application processor, the AX45MPV/NX27V for the vector/DSP processing and the N25/N225 processors as the resource and power manager. Leveraging the entire range of CPUs in the AndesCore™ families enables customers to streamline their development process, benefit from integrated support, and significantly reduce development cost.

The AX65 operates at speeds exceeding 2.0GHz on a 12nm process, boasting a SpecInt2006 score of 8.25 per GHz — outperforming the Cortex A75 with an efficient memory hierarchy. It also supports up to 8-core cache coherence with maximum 8MB shared cache. The AX65 is fully compliant with the RISC-V RVA22 profile, ensuring compatibility with operating systems and software within the RISC-V ecosystem. On the security side, AX65 supports Enhanced PMP (ePMP) for further securing memory accesses, and K (scalar cryptography) extension for accelerating AES and SHA crypto operations. For running Linux OS, the AX65 supports VIPT L1 instruction cache, SV48 virtual address space, and 2-level TLB with simultaneous hardware page walkers. It also incorporates state-of-the-art branch prediction mechanism with TAGE-L algorithm, return address stack and 2-level branch target buffer. The AX65 can be used as an application processor in networking applications like Wi-Fi, 5Gnr, and O-RAN, as well as in edge computing and industrial PCs. Furthermore, it is well-suited for serving as the primary controller processor in embedded applications.

“AX65 is our first out-of-order processor. It brings over 100% performance boost on SPECint2006 over the popular 45 Series processors. The successful launch of AX65 marks a quantum leap in performance of our processor lineup. With this proven OoO architecture, we can now target additional high-performance opportunities such as the main processors in AI/ML, Multimedia, Networking and Storage. That is very exciting for Andes,” said Dr. Charlie Su, President and CTO of Andes Technology.

“Among the RISC-V IP vendors, Andes delivered the first DSP-capable processor in D25F, the first vector processor in NX27V as well as the first functional safety processor with full ISO 26262 compliance in N25F-SE, and now they are all very successful in the market. Even though we are not the first for the out-of-order processor, we released it with a solid pace so that we do not need to reshuffle our teams along the way. Customers can trust Andes as a long-term supplier and partner for all their RISC-V CPU needs,” said Frankwell Lin, Chairman and CEO of Andes Technology.

Early customers in Asia, Europe and USA have been evaluating AX65 since August. Customers in multimedia and AI/ML have already signed up. The AX65 with Linux and RTOS support as well as development tools is available immediately for general licensing.

About Andes Webinar

Join us for an engaging webinar as we delve into the boundless possibilities of RISC-V architecture with a focus on the comprehensive Total Solutions offered by the Andes Series. Explore how these cutting-edge RISC-V CPU cores are reshaping the landscape of computing, powering innovations across diverse applications such as automotive and AI. Our experts will guide you through the features, advantages, and real-world applications of the Andes Processor Series, showcasing its ability to unlock the full potential of RISC-V technology. Whether you’re in the automotive industry or the AI sector, this webinar is your gateway to understanding how Andes Series Total Solutions can elevate your projects to new heights. Register now: https://zoom.us/webinar/register/WN_4KPwe_ljQgKxG14tSTgYbw

About Andes Technology

Eighteen years in business and a Founding Premier member of RISC-V International, Andes is a publicly-listed company (TWSE: 6533; SIN: US03420C2089; ISIN: US03420C1099) and a leading supplier of high-performance/low-power 32/64-bit embedded processor IP solutions, and the driving force in taking RISC-V mainstream. Its V5 RISC-V CPU families range from tiny 32-bit cores to advanced 64-bit Out-of-Order processors with DSP, FPU, Vector, Linux, superscalar, automotive and/or multi/many-core capabilities. By the end of 2022, the cumulative volume of Andes-Embedded™ SoCs has surpassed 12 billion. For more information, please visit https://www.andestech.com. Follow Andes on LinkedIn, Twitter, Bilibili and YouTube!

Continue ReadingAndes Announces General Availability of the New RISC-V Out-Of-Order Superscalar Multicore Processor, the AndesCore™ AX65

Andes Awards Imperas 2023 Partner of the Year

Imperas is honored for its support of Andes customers with Fast Processor Models of the Andes RISC-V processor IP

Oxford, United Kingdom, December 11, 2023 — Imperas Software Ltd., the leader in RISC-V simulation solutions, today announced that Andes Technology Corporation, a leading supplier of high efficiency, low-power 32/64-bit RISC-V processor cores and Founding Premier member of RISC-V International, has selected Imperas as the Andes Partner of the Year for 2023.  Imperas has worked with Andes since 2017 to provide fast, instruction accurate models for the complete range of Andes RISC-V processor IP, with Andes certifying Imperas models as reference models of the Andes cores. 

Virtual platforms (software simulation) are now a mainstream technology used to shift-left software development, and are also used after silicon is available for comprehensive, automated software testing.  The key requirement for the successful deployment of virtual platforms is quality models, especially of the processors.  In addition, the models need to be compatible with a range of industry standard tools and design flows, including SystemC and hardware emulators.  Imperas Fast Processor Models (ImperasFPMs) of the Andes processor IP satisfy these requirements. 

Andes provides a wide range of RISC-V CPUs, ranging from small microprocessors to multi-core applications processors with multi-issue out-of-order pipelines, including supporting the RISC-V DSP, FPU and vector extensions.  Andes was also the first company to develop a fully ISO 26262 compliant processor for automotive SoCs, including certification to the ASIL-B functional safety standard.  Andes processors are also used to meet high performance AI/ML requirements. 

Joint successes include a hyperscaler customer with a complex many-core AI accelerator. This customer used Imperas technology initially in their project for architecture exploration.  They then demonstrated their full software stack running within a week of receiving silicon, having developed the software in advance on Imperas virtual platforms with ImperasFPMs of the Andes processors. 

“Imperas provides high quality, fast simulation models, which enable our customers to develop highly complex software stacks ahead of silicon availability, improving their time to market and reducing risk,” said Dr. Emerson Hsiao, President, Andes Technology USA. “This award recognizes the strength of the partnership between Andes and Imperas.”

Dr. Emerson Hsiao, President,  Andes Technology USA presents the Partner of the Year award to Kat Hsu, Senior Account Manager, Imperas Software.

“As a founding member of RISC-V International, Andes has been driving the RISC-V instruction set architecture specification from the beginning, and their IP has set a very high standard for the community,” said Simon Davidmann, CEO at Imperas Software Ltd. “We have been supporting Andes customers with our models for nearly seven years, and feel honored to receive this Partner of the Year award as it recognizes the hard work and dedication of our entire team.” 

Availability

The Imperas models of the Andes processor IP portfolio are available now via www.OVPworld.org.  Imperas RISC-V reference models are also available via approved EDA distribution partners. To explore this option in more detail, please contact Imperas or your preferred EDA supplier.

About OVPworld.org

The Imperas simulation and modeling technology supports over 12 ISAs and over 300 processor models. OVPworld (Open Virtual Platforms) is dedicated to making software virtual platforms an easy and ubiquitous element of embedded software development. As the hardware has gotten more complex, the embedded software has also become more complex, and requires new tools. Software virtual prototypes, enabling embedded software simulation, verification and debug, are the key technology to effective embedded software development going forward.

OVP models are typically published under the Apache 2.0 open-source license and include reference platforms, examples and other collaborative projects from the community of OVP users. OVPworld was established over 10 years ago and has supported thousands of users, both commercial and academic. Registration is free, as is academic and non-commercial use, commercial users are supported for a 90-day evaluation period.

About Imperas

Imperas is the leading provider of RISC-V processor models, hardware design verification solutions, and virtual prototypes for software simulation. Imperas, along with Open Virtual Platforms (OVP), promotes open-source model availability for a spectrum of processors, IP vendors, CPU architectures, system IP and reference platform models of processors and systems ranging from simple single core bare metal platforms to full heterogeneous multi-core systems booting SMP Linux. All models are available from Imperas at www.imperas.com and the Open Virtual Platforms (OVP) website.

For more information about Imperas, please see www.imperas.com. Follow Imperas on LinkedIn, twitter @ImperasSoftware and YouTube.

About Andes Technology

Eighteen years in business and a Founding Premier member of RISC-V International, Andes is a publicly-listed company (TWSE: 6533; SIN: US03420C2089; ISIN: US03420C1099) and a leading supplier of high-performance/low-power 32/64-bit embedded processor IP solutions, and the driving force in taking RISC-V mainstream. Its V5 RISC-V CPU families range from tiny 32-bit cores to advanced 64-bit Out-of-Order processors with DSP, FPU, Vector, Linux, superscalar, automotive and/or multi/many-core capabilities. By the end of 2022, the cumulative volume of Andes-Embedded™ SoCs has surpassed 12 billion. For more information, please visit https://www.andestech.com. Follow Andes on LinkedIn, Twitter, Bilibili and YouTube!

All trademarks or registered trademarks are the property of Imperas Software Limited or their respective holders.

Continue ReadingAndes Awards Imperas 2023 Partner of the Year

Andes Technology Partners with WITTENSTEIN high integrity systems (WHIS) to Build Safety-Critical Solutions with RISC-V Processors

Nov. 13, 2023 – Andes Technology Corporation (TWSE: 6533), a leading supplier of high efficiency, low-power 32/64-bit RISC-V processor cores and Founding Premier member of RISC-V International, is pleased to announce its partnership with WITTENSTEIN high integrity systems. This partnership is geared towards assisting developers in creating safety-critical solutions utilizing RISC-V technology such as AndesCore™ N25F-SE and D25F-SE.

In 2022, Andes Technology made a ground-breaking milestone by introducing the world’s first ISO 26262 fully compliant RISC-V processor IP – N25F-SE. Andes is committed to providing unwavering support to automotive professionals in creating safety-critical product lines. With an extensive portfolio of AndesCore™ processors, Andes has catered to diverse needs, ranging from performance efficient MCUs to high-performance AI/ML computations. To meet the demands of a wide range of automotive applications, Andes not only offers ASIL-B certified processor IPs but also is working on mission-critical ASIL-D certified processor IPs based on its well-established and popular CPU IPs.

Andes Technology is set to release its next highly anticipated ISO 26262 fully compliant processor, the D25F-SE – the safety-enhanced D25F. The D25F CPU IP, one of the most popular cores from AndesCore™ 25-series, is equipped with RISC-V P-extension (SIMD/DSP) ISA draft to efficiently manipulate multiple data sets simultaneously in a single instruction. Many endpoint applications processing digital signals such as voice, audio, image, and sensors as well as machine learning algorithms could get performance boost by the efficient SIMD/DSP instruction set. The AndesCore™ D25F-SE has already attracted some early customers, and is expected to become available in 2023 Q4 for general licensing.

WITTENSTEIN high integrity systems (WHIS) is a safety systems company that produces and supplies real time operating systems (RTOS) and platform solutions to the Automotive, Medical and Industrial sectors worldwide. The exciting partnership with Andes Technology allows RISC-V developers to use the renowned safety critical RTOS SAFERTOS® from WHIS with the latest AndesCore™ processors. The SAFERTOS® has been independently certified by TÜV SÜD to IEC 61508 SIL3 and ISO 26262 ASIL-D. It is used internationally wherever safety is paramount, delivering superior performance and reliability. Delivered with full source code and Design Assurance Pack, the SAFERTOS® is tailored for the customer’s unique processor/compiler combination and is very popular due to its impressive safety credentials and a straightforward upgrade path from the FreeRTOS, industry’s most popular open-source RTOS.

SAFERTOS® fully functional demos are available on the Andes development boards. Try SAFERTOS® for free today at: https://www.highintegritysystems.com/down-loads/manuals-datasheets/safertos-datasheet-downloads/. Andes development boards can be found for purchase on Mouser. For more information, please visit https://www.andestech.com/en/products-solutions/andeshape-platforms/.

“We’re proud to partner with Andes Technology and for SAFERTOS® to support AndesCore™.” said Andrew Longhurst, Managing Director for WITTENSTEIN high integrity systems. “We see a strong, compelling case for SAFERTOS® to support the RISC-V architecture. This combination of both technologies will provide an ideal platform for safety critical projects in the future.”

“The functional safety AndesCore™ IPs offer unique and competitive value to our customers demanding RISC-V processors with full certification,” said Dr. Charlie Su, Andes Technology’s President and CTO. “The exciting partnership with WITTENSTEIN high integrity systems enables us to provide solid solutions to our customers who are developing products for safety-critical applications. We are thrilled to partner with WITTENSTEIN high integrity systems as they bring the advantages of the SAFERTOS® to the RISC-V community, thereby enhancing the performance and robustness of safety-related RISC-V applications.”

About Andes Technology

Eighteen years in business and a Founding Premier member of RISC-V International, Andes is a publicly-listed company (TWSE: 6533; SIN: US03420C2089; ISIN: US03420C1099) and a leading supplier of high-performance/low-power 32/64-bit embedded processor IP solutions, and the driving force in taking RISC-V mainstream. Its V5 RISC-V CPU families range from tiny 32-bit cores to advanced 64-bit Out-of-Order processors with DSP, FPU, Vector, Linux, superscalar, and/or multi/many-core capabilities. By the end of 2022, the cumulative volume of Andes-Embedded™ SoCs has surpassed 12 billion. For more information, please visit https://www.andestech.com. Follow Andes on LinkedIn, Twitter, Bilibili and YouTube!

About WITTENSTEIN high integrity systems

WITTENSTEIN high integrity systems is an RTOS company that specialises in safety, producing and supplying Real-time Operating Systems and Software Components to the Automotive, Medical, Aerospace and Industrial sectors worldwide. For more information, please visit: https://www.highintegritysystems.com

Continue ReadingAndes Technology Partners with WITTENSTEIN high integrity systems (WHIS) to Build Safety-Critical Solutions with RISC-V Processors

Andes and Vector Propel RISC-V AUTOSAR Software Innovations for the Automotive Industry

Hsinchu, Taiwan and Stuttgart, Germany – Nov. 6, 2023 – Andes Technology, the renowned supplier of high-efficiency, low-power 32/64-bit RISC-V processors and a Founding Premier member of RISC-V International, and Vector, the specialist for software and automotive electronics development, are excited to announce a collaboration aimed at advancing automotive software solutions with the RISC-V architecture. This cooperation unites the expertise of two industry leaders, enabling the development of integrated automotive solutions combining AndesCore™ Safety-Enhanced (SE) RISC-V processor series and Vector’s MICROSAR Classic basic software, accelerating innovation and time-to-market.

Andes, the first RISC-V CPU vendor to deliver an ISO-26262 fully compliant core N25F-SE, keeps advancing in the automotive market by executing a rich FuSa processor roadmap that additionally includes the DSP-enabled D25F-SE, the compact and secure D23-SE, the high-performance D45-SE, and the ADAS-capable 60-SE Series. With its state-of-the-art RISC-V CPU architecture, AndesCore™ brings flexibility and scalability to the world of automotive processors, and delivers exceptional performance, energy efficiency, and safety to meet the specific requirements of various automotive applications.

Vector is a leading provider of AUTOSAR software for the automotive industry. As a Premium Partner Plus (PP+), Vector is taking on extended steering tasks within the well-known development partnership. Vector is thus helping to shape the strategic direction of AUTOSAR, to ensure the performance of the standard for future ECU development, such as in the Software-Defined Vehicle (SDV).

“The automotive industry is at a pivotal juncture to aggressively incorporate fast-growing E/E and AI technologies. At the same time, RISC-V is the emerging computing architecture that is becoming a mainstream in every segment from edge to cloud. It’s momentous that we work together to drive innovation and meet the challenges of automotive applications,” said Simon Wang, Senior Technical Marketing Manager of Andes. “Our collaboration with Vector is a significant step in that direction, offering an integrated solution that will facilitate the automotive industry’s progression into the future.”

“We are excited to work with Andes and combine our AUTOSAR software expertise with their advanced RISC-V processors. This collaboration will enable our MICROSAR products to run on RISC-V-based processors and create state-of-the-art, safe and efficient systems that can thrive in the dynamic automotive landscape,” said Nöbauer, Josef, Senior Manager and Head of Embedded SW Product Development for “Semiconductor Platforms and MCAL” at Vector Informatik.

About Andes Technology
Eighteen years in business and a Founding Premier member of RISC-V International, Andes is a publicly-listed company (TWSE: 6533; SIN: US03420C2089; ISIN: US03420C1099) and a leading supplier of high-performance/low-power 32/64-bit embedded processor IP solutions, and the driving force in taking RISC-V mainstream. Its V5 RISC-V CPU families range from tiny 32-bit cores to advanced 64-bit Out-of-Order processors with DSP, FPU, Vector, Linux, superscalar, functional safety and/or multi/many-core capabilities. By the end of 2022, the cumulative volume of Andes-Embedded™ SoCs has surpassed 12 billion. For more information, please visit https://www.andestech.com.

About Vector
Vector is the leading manufacturer of software tools and embedded components for the development of electronic systems and their networking with many different systems from CAN to Automotive Ethernet. Vector has been a partner of automotive manufacturers and suppliers and related industries since 1988. Vector tools and services provide engineers and software developers with the decisive advantage to make a challenging and highly complex subject area as simple and manageable as possible. Vector employees work on electronic innovations for the automotive industry every day. Worldwide customers in the automotive, commercial vehicles, aerospace, transportation, and control technology industries rely on the solutions and products of the independent Vector Group for the development of technologies for future mobility. Vector is headquartered in Germany (Stuttgart) and has subsidiaries in Brazil, China, France, Great Britain, India, Italy, Japan, Austria, Romania, Sweden, South Korea, Spain and the USA.

Continue ReadingAndes and Vector Propel RISC-V AUTOSAR Software Innovations for the Automotive Industry

TASKING, Andes, and MachineWare Team Up to Facilitate Rapid Development of RISC-V ASIL Compliant Automotive Silicon

To support SoC design teams in the realm of firmware and MCAL development

Munich, Germany – Nov. 6, 2023 – TASKING’s system-level verification and debugging tools now support the Andes RISC-V ISO 26262 certified Processor IPs and associated MachineWare Virtual Models. This collaboration equips SoC design teams with automotive-grade RISC-V IPs and the appropriate tools for early firmware and MCAL (Microcontroller Abstraction Layer) development.

TASKING has been serving the global automotive industry for more than 30 years with software development tools certified for functional safety and cybersecurity. The toolset released as part of the collaboration provides the capabilities for multi-core, multi-hart, verification, debugging, performance tuning, timing, and coverage analysis. The toolset can be used with Andes RISC-V development boards and MachineWare high-performance virtual prototyping solutions. Moreover, the innovative TASKING iSYSTEM debug adapters will be available to support Andes RISC-V processors to enable the connection with the toolset.

Andes Technology, a prominent provider of high-efficiency, low-power 32/64-bit RISC-V processor cores, introduced the first ISO 26262 fully compliant RISC-V processor IP – N25F-SE in 2022 with ASIL-B certification. Andes is also gearing up to unveil the ASIL-B certified D25F-SE equipped with RISC-V P-extension (SIMD/DSP) ISA draft for efficient manipulation of multiple data in a single instruction in the fourth quarter of 2023. Furthermore, Andes is working to deliver mission-critical ASIL-D certified cores based on their popular CPU IPs. The goal of this partnership is to offer comprehensive support for functional safety solution development, particularly in the realm of firmware and MCAL development. These resources will subsequently be employed by their customers within the automotive supply chain.

MachineWare’s ultra-fast virtual prototypes facilitate simulation of complex hardware/software systems for software analysis, verification and development as well as architecture exploration. With SIM-V MachineWare offers a high-speed RISC-V simulator that can be integrated in a full-system simulation, or Virtual Platform (VP) to simulate entire SoCs or ECUs. Besides pre-silicon availability, VPs offer many advantages over physical prototypes, as they enable for deep, non-intrusive introspection and are extremely scalable either on-premise or in the cloud.

The combination of products from the three companies enables users to switch seamlessly between virtual and physical SoCs, applying the same tools and automation scripts without any changes to the users’ process. This allows software developers to start the development process before silicon is available and identify and fix potential bugs and security issues at an early stage, shortening time-to-market.

Gerard Vink, responsible for RISC-V at TASKING, is excited about the collaboration of the three companies: “This partnership offers an integrated solution needed to drive the adoption of RISC-V based SoCs in the automotive domain. The certified IPs and tools reduce the efforts of all parties in the supply chain to comply with functional safety and cybersecurity requirements, enabling them to focus on innovation and product differentiation.”

“Andes’ ISO 26262 certified RISC-V IP offers solid, unprecedented flexibility and efficiency in silicon development,” said Samuel Chiang, Deputy Marketing Director of Andes, “Together with TASKING and MachineWare, we empower customers in the automotive industry to accelerate their development efforts, ensuring the successful achievement of functional safety and cybersecurity protection.”

“Our ultra-fast SIM-V functional RISC-V simulator empowers engineers to simulate complex hardware/software systems long before physical prototypes are even available. This speeds up the development process and reduces expensive bugs,” said Lukas Jünger, co-founder of MachineWare. “We are proud to collaborate with TASKING and Andes to offer our customers the tools they need for developing SoCs for the automotive industry.”

For more detailed information about the partnership and the three companies, please visit www.tasking.com, www.andestech.com and www.machineware.de.

About Andes Technology
Eighteen years in business and a Founding Premier member of RISC-V International, Andes is a publicly listed company  (TWSE: 6533; SIN: US03420C2089; ISIN: US03420C1099), a leading supplier of high-performance/ low-power 32/64-bit embedded processor IP solutions, and the driving force in taking RISC-V mainstream. Its V5 RISC-V CPU families range from tiny 32-bit cores to advanced 64-bit Out-of-Order processors with DSP, FPU, Vector, Linux, superscalar, and/or multi/many-core capabilities. By the end of 2022, the cumulative volume of Andes-Embedded™ SoCs has surpassed 12 billion. For more information, please visit https://www.andestech.com. Follow Andes on LinkedIn, Twitter, Bilibili and YouTube! 

About MachineWare
Established in 2022 in Aachen, Germany, MachineWare is a pioneering company specializing in the creation of high-performance simulators for entire electronic systems, commonly referred to as Virtual Platforms (VPs). These cutting-edge VPs are designed to execute unmodified target software, serving as indispensable tools for development, verification, and architecture exploration.

One of MachineWare’s flagship offerings, SIM-V, stands out as a versatile and rapid solution tailored for virtualizing RISC-V systems. SIM-V empowers users to accelerate their RISC-V software development process, allowing them to meet and exceed their schedules by helping to identify software defects, such as bugs and vulnerabilities long before physical prototypes are available.

MachineWare’s products and services simplify hardware/software integration by providing a unified toolset for both hardware and software designers early in the system design cycle. This approach facilitates a smoother development process and superior end products. Visit https://www.machineware.de for more details.

About TASKING
TASKING is a leading provider of development tools headquartered in Munich, Germany, offering high-performance, high quality, safety & security-oriented embedded software development tools for multi-core architectures.

TASKING’s development tools are used by automotive manufacturers and suppliers, as well as in adjacent markets around the world to realize high-performance applications in safety-critical areas.

The TASKING Embedded Software Development solutions provide an industry-leading ecosystem for your entire software development process. Each TASKING compiler is designed for a certain architecture and meets the specific requirements of your industry, including automotive, industrial, telecommunications and datacom.

As the recognized leader in high-quality, feature- and safety-compliant embedded software development tools, TASKING enables you to create code with best-in-class size and performance with compilers, debuggers and RTOS support for industry-leading microprocessors and microcontrollers.

Since February 2021, TASKING has been majority-owned by financial investor FSN Capital, which has put the group on a long-term growth path following a successful carve-out. For more information visit www.tasking.com or follow us on https://www.linkedin.com/company/tasking-inc.

Continue ReadingTASKING, Andes, and MachineWare Team Up to Facilitate Rapid Development of RISC-V ASIL Compliant Automotive Silicon

Ansys medini Accelerates Andes’ Development of Automotive-Grade IP

Hsinchu, Taiwan – Nov. 2, 2023 – The automotive industry imposes stringent requirements on Functional Safety. For semiconductor companies involved in automotive chips and even further upstream in Silicon Intellectual Property (SIP), obtaining ISO 26262 certification is a fundamental requirement for product penetration into automotive applications. Andes Technology is actively developing a portfolio of automotive-grade IP products to enhance the efficiency of product functional safety verification activities. To streamline ISO 26262 verification and to integrate verification information conveniently, the decision was made to introduce Ansys medini to achieve the automation and modulization of safety analysis process.

In the field of RISC-V CPU IP for the automotive market, Andes Technology has achieved remarkable milestones. In 2020, Andes became the world’s first RISC-V supplier to have its development process certified to ISO-26262 ASIL-D standard. In 2022, Andes became the world’s first RISC-V supplier to have its IP fully certified to ISO-26262 ASIL-B standard, with the solution adopted in over ten customer projects. Andes is proactively addressing the demands of the automotive market by planning a comprehensive range of automotive IP products, covering RISC-V IP solutions with different functional safety levels from ASIL-B to ASIL-D, along with varying processor performance levels and feature sets. In 2023, Andes is set to officially introduce an 8-stage pipeline dual-issue processor that meets the ASIL-D standard. This signifies their ability to provide tailored solutions for diverse automotive applications, highlighting their leading expertise in the automotive RISC-V IP market. Adopting Ansys medini is an important step in this direction.

Eric Huang, Associate Vice President of Quality and Safety Management at Andes Technology, pointed out that for players in the automotive supply chain, obtaining certifications such as ISO 26262 is a critical factor determining market entry and approving technical strength. For IP suppliers to attain these certifications, two main challenges need to be addressed: the first is to introduce the complicated and rigorous ISO 26262 requirements efficaciously. The second is to develop and actualize the safety features competitively. The more products are developed for automotive market, the more crucial is to boost the safety analysis efficiency to speed up design verification.

Dr. Alex Chen, Director of the VLSI at Andes Technology, pointed out that the design verification process often involves the use of various analysis tools, such as FMEDA and FTA. However, the documents generated by these tools are typically stored in different formats and dispersed. This process is highly cumbersome and necessitates constant checks to ensure data consistency and accuracy. In the event of data changes, manual effort is needed to update the data, making it a mental-intensive activity.

Therefore, having an automated tool that can link the documents generated by different analysis tools and consistently update them to the latest versions is important for developing automotive-grade IP. Ansys medini provides an integrated environment that not only includes the analysis tools required by standards like ISO 26262 but also automates data transfer. This not only eases the loading on document verification but also enhances the accuracy of related data. As a result, Andes IP solutions can obtain ISO 26262 certification more quickly.

“The innovation cycle in the automotive industry is accelerating, but the requirements for functional safety are non-negotiable. Therefore, whether it’s automotive OEMs, Tier 1, Tier 2, or semiconductor companies further upstream, they are all seeking automation tools that can expedite functional safety analysis and verification processes.” Roger Lee, Ansys Taiwan Country Manager, stated. “Currently, there are many standalone tools in the market that meet the specific requirements of individual ISO 26262 verification items. However, Ansys medini is the only tool that can further achieve data integration and interfacing, enabling comprehensive automation of data generation, consolidation, and maintenance, with the added benefit of data reuse. This unique advantage has gained widespread recognition and adoption throughout the automotive industry’s supply chain. There are high expectations that Ansys medini will bring enhanced competitiveness to Andes Technology’s automotive-grade IP business.”

About Andes Technology
Eighteen years in business and a Founding Premier member of RISC-V International, Andes is a publicly-listed company (TWSE: 6533; SIN: US03420C2089; ISIN: US03420C1099) and a leading supplier of high-performance/low-power 32/64-bit embedded processor IP solutions, and the driving force in taking RISC-V mainstream. Its V5 RISC-V CPU families range from tiny 32-bit cores to advanced 64-bit Out-of-Order processors with DSP, FPU, Vector, Linux, superscalar, and/or multi/many-core capabilities. By the end of 2022, the cumulative volume of Andes-Embedded™ SoCs has surpassed 12 billion. For more information, please visit https://www.andestech.com. Follow Andes on LinkedIn, Twitter, Bilibili and YouTube! 

Continue ReadingAnsys medini Accelerates Andes’ Development of Automotive-Grade IP

Andes Technology to Exhibit Groundbreaking RISC-V Solutions for AI and Automotive at RISC-V Summit North America 2023

Discover the cutting-edge insights from Andes’ presentations and explore live demonstrations of CPU IP technology at Booth #D4 and get your opportunity to seize lucky draw prizes, including mobile phones!

SAN JOSE, CA – Oct. 31, 2023 – Andes Technology Corporation (TWSE: 6533), a leading provider of high efficiency, low-power 32/64-bit RISC-V processor cores and a Founding Premier member of RISC-V International, announces its significant role as the diamond sponsor in RISC-V Summit North America, the prestigious annual event held from November 6 to 8, 2023 in Santa Clara. As a key contributor, Andes will deliver a keynote speech about AI/ML SoC solutions based on RISC-V and the latest on Andes RISC-V processors to enable them. Andes will also address three presentations and two demo talks focused on AI/ML solutions, automotive-grade IP, IOPMP, RISC-V vector technology and more. During the event, Andes will showcase its state-of-the-art RISC-V CPU IP offerings at booth #D4.

Andes President and CTO, Dr. Charlie Su, will present why RISC-V is a perfect solution to bring intelligence everywhere and introduce Andes product portfolio in the keynote speech “Taking RISC-V Intelligence Everywhere” on November 8 at 9:55 AM. Dr. Paul Ku, Deputy Director of Andes and chair of IOPMP task group, will give an update of IOPMP spec on November 6 at 14:55 PM. Chun-Nan Ke, Senior Technical Manager, will explore the Andes proposal for RISC-V matrix multiplication instructions which enhance significant performance for AI applications in his presentation “Advancing AI Computing with Optimized Matrix Multiplication Techniques with RISC-V CPU” on November 7 at 12:10 PM. Furthermore, Dr. Heng-Kuan Lee, Senior Manager, will discuss how to enhance efficiency and accuracy of computations in transformer models in “Enhancing Transformers: Accelerating Nonlinear Function Computation on RISC-V Vector Processor” on November 7 at 15:15 PM. Lastly, Hubert Chung, FAE Manager, will deliver a demo talk “AI Solution – AndesAIRE, including HW and SW” on November 7 at 12:55 PM . Marvin Chao, Director of Solution Architect, will give the other demo talk “Andes Technology RISC-V Functional Safety Solutions” on November 7 from 11:10 to 11:20 AM at the demo theater.

In addition, Andes will proudly display development boards integrated with Andes-Embedded™ technology at the Developer Zone. These boards include the Tinker V, the first RISC-V Single-Board Computer (SBC) from ASUS IoT; an MPU development board from Renesas; high-performance industrial-grade microcontrollers from HPMicro; one of the first complete RISC-V microcontrollers with an embedded FPGA from Gowin; and an Arduino-compatible development board based on a wireless SoC from Andes. Seize the opportunity to understand how customers are working with Andes products for various applications by visiting the Developer Zone. Also, Andes will announce its new safety-enhanced core, D25F-SE, at the Launchpad session.

Besides presentations and live demo, RISC-V Board of Director and Andes CEO, Frankwell Lin, will join the Media Panel Luncheon “RISC-V is HERE: Future Outlook with Invested RISC-V Leaders” on November 7 at 13:00 PM. Join the discussion to discover the remarkable progress in the RISC-V ecosystem across diverse applications and witness how RISC-V is empowering companies with advanced design flexibility.

This event presents a valuable opportunity for RISC-V enthusiasts to reserve one-on-one discussion with Andes experts to explore RISC-V solutions in-depth. Andes invites you to visit booth #D4 at the RISC-V Summit and experience live demonstrations of its leading-edge CPU IP technology. Stop by Andes’ booth for a chance to win fantastic prizes, including mobile phones!

Details of Andes’ sessions during the RISC-V Summit are outlined below:

  • November 6 (Member Day),
    • 14:55-15:20 PM: Presentation “IOPMP Update” by Dr. Paul Ku, Deputy Technical Director
  • November 7 (Day 1),
    • 12:10-12:30 PM: Presentation “Advancing AI Computing with Optimized Matrix Multiplication Techniques with RISC-V CPU” by Chun-Nan Ke, Senior Technical Manager, and Dr. Heng-Kuan Lee, Senior Manager
    • 13:00-13:55 PM: Media Panel Luncheon “RISC-V is HERE: Future Outlook with Invested RISC-V Leaders” by Frankwell Lin, Chairman and CEO
    • 12:55-13:05 PM: Demo “AI Solution – AndesAIRE, including HW and SW” by Hubert Chung, FAE Manager
    • 15:15-15:35 PM: Presentation “Enhancing Transformers: Accelerating Nonlinear Function Computation on RISC-V Vector Processor” by Dr. Heng-Kuan Lee, Senior Manager, and Simon Wang, Senior Technical Manager
  • November 8 (Day 2),
    • 9:55-10:10 AM: Keynote “Taking RISC-V Intelligence Everywhere” by Charlie Su, CTO and President
    • 11:10-11:20 AM: Demo “Andes Technology RISC-V Functional Safety Solutions” by Marvin Chao, Director of Solution Architect

For more information, please visit the RISC-V Summit website.

About Andes Technology
Eighteen years in business and a Founding Premier member of RISC-V International, Andes is a publicly-listed company (TWSE: 6533; SIN: US03420C2089; ISIN: US03420C1099) and a leading supplier of high-performance/low-power 32/64-bit embedded processor IP solutions, and the driving force in taking RISC-V mainstream. Its V5 RISC-V CPU families range from tiny 32-bit cores to advanced 64-bit Out-of-Order processors with DSP, FPU, Vector, Linux, superscalar, and/or multi/many-core capabilities. By the end of 2022, the cumulative volume of Andes-Embedded™ SoCs has surpassed 12 billion. For more information, please visit https://www.andestech.com. Follow Andes on LinkedIn, Facebook, Weibo, Twitter, Bilibili and YouTube! 

Continue ReadingAndes Technology to Exhibit Groundbreaking RISC-V Solutions for AI and Automotive at RISC-V Summit North America 2023

Andes Technology Unveils Andes D23 and N225 Cores Pioneering the Next Generation of Compact, Performant, and Secure RISC-V Processor Technology

Hsinchu, Taiwan – Oct. 17, 2023 – Andes Technology, the renowned supplier of high-efficiency, low-power 32/64-bit RISC-V processor cores and a Founding Premier member of RISC-V International, proudly announces the release of its latest innovation – the AndesCore™ D23 and N225 RISC-V processors. Specifically designed to cater to the dynamic needs of the Internet of Things (IoT) and embedded systems, these cores epitomize Andes’ unwavering commitment to delivering cutting-edge technology for the interconnected world.

The D23 and N225 cores have been meticulously engineered with compactness, performance-efficiency, low-power consumption, flexibility, and security as top priorities. These cores empower IoT and embedded chip and device manufacturers to meet the burgeoning demands of a rapidly evolving market while minimizing power usage and ensuring robust security.

Andes announced the popular N22, a 2-stage pipeline AndesCore implementing RV32I/EMAC ISA back in February 2019, targeting deeply embedded processing and having a performance of 3.95 Coremark/MHz and 1.8 DMIPS/MHz. The D23 and N225 are revamped designs with a new microarchitecture and the latest RISC-V extensions (details below) to offer better performance, smaller code size, and more security support. They provide a good migration path for customers looking to upgrade their N22 designs or kick-off a new design today.

Common Key Features of AndesCore D23 and N225:
Latest RISC-V Extensions Support: The N225 implements the RV32 IMACBZce non-privileged extensions as well as Machine/User modes and Enhanced Physical Memory Protection (ePMP). The D23 additionally supports the FDKP extensions (Single/Double-Precision Floating-Point, Scalar Crypto and Packed SIMD/DSP draft), and CMO (Cache Management Operations) extension. The D23 is also incorporated with Supervisor mode and its associated PMP (sPMP) for higher security.

Compact Size: Both cores feature a highly compact design with a 3-stage pipeline, primarily supporting single instruction issue with some dual-issue capability. This makes them exceptionally well-suited for space- and memory-constrained IoT and embedded applications, including wearables, sensors, and smart home devices.

High Performance: Both cores achieve industry-leading performance in their class, boasting outstanding benchmark scores such as 4.55 (D23) and 4.4 (N225) Coremark/MHz, and 2.08 (D23) and 1.92 (N225) DMIPS/MHz, respectively. They are capable of operating at high frequencies across various technology nodes such as near 800 MHz at 28nm, providing the necessary computing power for edge IoT devices with ever-increasing performance and feature demands.

Power Management: Both cores support advanced power management technologies such as PowerBrake and Wait-For-Interrupt (WFI) and Wait-For-Event (WFE), ensuring prolonged battery life for many types of untethered IoT devices.

Small Code Size: The N22 already offers industry-leading code size with Andes CoDense™ technology. With the addition of the new RISC-V Zce code size reduction extension, the D23 and N225 further reduce 4.4% code size for the Embench-IoT benchmark, compared to the N22. This provides additional memory cost-saving for Andes customers.

Flexibility: Both cores offer extensive configurability, including optimized multipliers for performance or area, optional static or dynamic branch prediction, various combinations of privilege modes, instruction and data Local Memories with sizes from 1 KB to 512 MB, and 2-wire or 4-wire JTAG debug interface. Designers can tailor these features to address their specific application requirements.

Ease of SoC Integration: To simplify integration into System-on-Chip (SoC) designs, both cores support either Core-Local Interrupt Controller (CLIC) for the single-CPU SoC or Platform-level Interrupt Controller (PLIC) for multiple-CPU SoC, rich options for AMBA interfaces, private machine timers or platform machine timers, and instruction trace interfaces.

In addition to the above-mentioned shared features and latest RISC-V extensions, the D23 core boasts additional capabilities, including built-in instruction and data caches, and ECC soft error protection for all cache and local memories. It can also seamlessly integrate with the powerful ACE™ (Andes Custom Extension) to support custom instructions for Domain-Specific Acceleration (DSA) and has a roadmap to include a functional safety derivative. These expanded capabilities open up opportunities for the D23 to serve a wider range of segments in automotive and industrial control applications.

Dr. Charlie Su, President and CTO of Andes Technology, expressed his enthusiasm for the release of these cores, stating, “The D23 and N225 mark a significant milestone in our commitment to providing innovative solutions for the IoT and embedded segments. With their compact design, power efficiency, and robust security features, these cores are poised to set new industry standards. We believe they will empower designers and developers to create cutting-edge products that can thrive in the fast-paced world of IoT.”

The D23/N225 have been licensed out and several companies are actively evaluating them. Their overall features will be developed and delivered in two phases. For more information about these cores, please visit the Andes Technology website.

About Andes Technology
Eighteen years in business and a Founding Premier member of RISC-V International, Andes is a publicly-listed company (TWSE: 6533; SIN: US03420C2089; ISIN: US03420C1099) and a leading supplier of high-performance/low-power 32/64-bit embedded processor IP solutions, and the driving force in taking RISC-V mainstream. Its V5 RISC-V CPU families range from tiny 32-bit cores to advanced 64-bit Out-of-Order processors with DSP, FPU, Vector, Linux, superscalar, and/or multi/many-core capabilities. By the end of 2022, the cumulative volume of Andes-Embedded™ SoCs has surpassed 12 billion. For more information, please visit https://www.andestech.com. Follow Andes on LinkedIn, Twitter, Bilibili and YouTube! 

Continue ReadingAndes Technology Unveils Andes D23 and N225 Cores Pioneering the Next Generation of Compact, Performant, and Secure RISC-V Processor Technology