Andes Announces General Availability of the New AndesCore™ RISC-V Multicore Vector Processor AX45MPV

Hsinchu, Taiwan – Sep. 7, 2023 –  Andes Technology, a leading supplier of high efficiency, low-power 32/64-bit RISC-V processor cores and Founding Premier member of RISC-V International, today proudly announces general availability of the high-performance AndesCore™ AX45MPV multicore vector processor IP. The AX45MPV is the third generation of the award winning AndesCore™ vector processor series. Equipped with powerful RISC-V vector processing and parallel execution capability, it targets the applications with large volumes of data such as ADAS, AI inference and training, AR/VR, multimedia, robotics, and signal processing.

Andes and Meta started collaboration on datacenter AI with RISC-V vector core from early 2019*(See Remarks). Andes later unveiled the AndesCore™ NX27V, marking a significant milestone as the industry’s first commercial RISC-V vector processor core with the capability of generating up to 4 512-bit vector (VLEN) results per cycle, at the end of 2019. It immediately attracted the attention of worldwide SoC design teams working on AI accelerators, and has landed over a dozen datacenter AI projects. Since then, the RISC-V vector processor cores have become the choice for ML and AI chip vendors.

With the goal to further raise the compute density, the AX45MPV extends the capabilities of the dual-issue 8-stage pipeline, Linux support and multicore of the AX45MP with the powerful vector processing unit inherited and enhanced from its predecessor, the NX27V. While the AX45MPV is essentially a Linux application processor with datacenter grade AI capabilities, its support for Linux and multicore can be left out to form an efficient and powerful compute processor in processing elements (PEs) of a large compute array.  The dual-issue capability combined with up to 6 1024-bit vector (VLEN) results per cycle in the AX45MPV can provide more than 3X performance comparing with its predecessor. To fully exploit its higher computation power, the AX45MPV offers two 1024-bit memory interfaces. The new high-bandwidth vector local memory (HVM) option provides 1 or 2 HVM bank ports, ideal for vector loads/stores, and an external DMA engine to move chunks of data in the background through an AXI-based HVM Access Port. For computation tasks requiring an integrated coprocessor control along with data transfer, the versatile Andes Streaming Port (ASP) available since the first Andes vector processor is the best solution.  By combining the ASP and the HVM ports, the processor effectively doubles its memory bandwidth by, say, being able to load 2 vector data per cycle. The AX45MPV also supports the latest ACE (Andes Custom Extension™), which facilitates customers to create their own RISC-V styled vector instructions.  For example, ACE can be used to accelerate nonlinear math functions such as SoftMax on Transformer AI.

“Andes has been serving datacenter AI customers since 2019 with RISC-V Vector architecture and has accumulated rich experience. Equipped with the powerful 1024-bit vector unit, efficient support of multicore and Linux, and versatile configurations, the third generation of Andes vector processors AX45MPV is specially tailored for Large Language Models (LLMs). With the surge of generative AI applications in 2023, we see the AX45MPV taking the center stage in AI and Machine Learning segments beyond the Cloud.”, said Dr. Charlie Su, President and CTO of Andes Technology.

Some customers from Asia and North America have already licensed the AX45MPV, and more are evaluating it. Their applications cover a wide range from the cloud to the edge. The AX45MPV standard product package, without Linux support, is available immediately. Its advanced product package will come with Linux support and will be available in Q4 2023.

 

About Andes Technology
Eighteen years in business and a Founding Premier member of RISC-V International, Andes is a publicly-listed company (TWSE: 6533; SIN: US03420C2089; ISIN: US03420C1099) and a leading supplier of high-performance/low-power 32/64-bit embedded processor IP solutions, and the driving force in taking RISC-V mainstream. Its V5 RISC-V CPU families range from tiny 32-bit cores to advanced 64-bit Out-of-Order processors with DSP, FPU, Vector, Linux, superscalar, and/or multi/many-core capabilities. By the end of 2022, the cumulative volume of Andes-Embedded™ SoCs has surpassed 12 billion. For more information, please visit https://www.andestech.com. Follow Andes on LinkedIn, Twitter, Bilibili and YouTube! ! 

*Remarks: MTIA: First Generation Silicon Targeting Meta’s Recommendation Systems, ISCA ’23: Proceedings of the 50th Annual International Symposium on Computer Architecture, June 2023

Continue ReadingAndes Announces General Availability of the New AndesCore™ RISC-V Multicore Vector Processor AX45MPV

GOWIN Semiconductor & Andes Technology Corp. Announce The First RISC-V CPU and Subsystem Ever Embedded 22nm SoC FPGA

GOWIN Is Offering the Andes A25 RISC-V CPU IP and AE350 Subsystem
As Instantiated Hard Cores in Its GW5AST-138 FPGA

San Jose, CA – Aug. 29, 2023 – Andes Technology Corporation (TWSE: 6533), a leading supplier of high efficiency, low-power 32/64-bit RISC-V processor cores and Founding Premier member of RISC-V International, is thrilled to announce that its AndesCore™ A25 RISC-V CPU IP and AE350 peripheral subsystem is hardened and embedded in the GW5AST-138 FPGA chip from GOWIN Semiconductor, the world’s fastest growing FPGA company. This integration, one of the first complete RISC-V microcontrollers in an FPGA, provides designers the A25 processor power and the peripherals most processors require without consuming any FPGA resources. Thus, the hardware team can populate the FPGA with their value-added design while the software team can concurrently create application code based on the rich RISC-V ecosystem.

“Andes is committed to delivering cutting-edge RISC-V technologies allowing developers to create innovative and efficient solutions. The integration of the A25 RISC-V CPU and AE350 peripheral subsystem as a hard core in GOWIN Semiconductor’s GW5AST-138 FPGA marks a significant milestone in achieving this vision,” said Andes North America VP of Sales, Vivien Lin.  “This represents a significant milestone for the RISC-V architecture as it provides our joint customers a versatile hardware development platform to create, debug, and verify their ultimate SoC design before committing their netlist for silicon fabrication. For customers not requiring an SoC, it will enable a complete RISC-V computer ready to drive their end applications.”

“In the Arora V family, we incorporate the peripherals that a RISC-V CPU typically requires in hard instantiations,” says GOWIN’s Sr. Director of Solution Development, Jim Gao. “We included a fully controllable high-speed SerDes for communication, video aggregation, and AI computing acceleration applications that demand very high data rates. Other instantiated functions include Block RAM modules supporting ECC error correction, high-performance multiple voltage GPIO, and high accuracy clock architecture. These hard functions save the FPGA programmable fabric of up 138K LUT’s for the designers’ unique logic implementation.”

About the RISC-V Based GW5AST-138 FPGA:
The AndesCore™ A25 hard core, running at 400MHz, supports the RISC-V P-extension DSP/SIMD ISA (draft), single- and double-precision floating point and bit-manipulation instructions, and MMU for Linux based applications. The AE350 AXI/AHB-based platform comes with level-one memories, interrupt controller, debug module, AXI and AHB Bus Matrix Controller, AXI-to-AHB Bridge and a collection of fundamental AHB/APB bus IP components pre-integrated together as a system design. DDR3 controller and SPI-Flash controller in the FPGA fabric back up the A25’s 32KByte I-Cache and D-Cache after cache misses. Off chip DDR3 provides data memory, SPI-Flash contains the A25’s instruction memory (codes copied from SPI-Flash into DDR3 and Cache upon boot-up).  Besides hard instantiated functions, the GOWIN GW5AST-138 FPGA fabric affords 138K LUTs for custom design implementation.  GOWIN EDA provides an easy-to-use FPGA hardware development environment for the Arora V.  The environment supports multiple RTL-based programming languages, synthesis, placement and routing, bitstream generation and download, power analysis and in-device logic analyzer.

GOWIN PR

Price & Availability
The GW5AST-138 FPGA with SDK with GOWIN_V1.9.9 Beta-3 will be available August 18 through distribution.

About GOWIN Semiconductor Corp.
Founded in 2014, GOWIN Semiconductor Corp., headquartered with major R&D in China, has the vision to accelerate customer innovation worldwide with our programmable solutions. We focus on optimizing our products and removing barriers for customers using programmable logic devices. Our commitment to technology and quality enables customers to reduce the total cost of ownership from using FPGA on their production boards. Our offerings include a broad portfolio of programmable logic devices, design software, intellectual property (IP) cores, reference designs, and development kits. We strive to serve customers in the consumer, industrial, communication, medical, and automotive markets worldwide.

About Andes Technology
Eighteen years in business and a Founding Premier member of RISC-V International, Andes is a publicly listed company  (TWSE: 6533; SIN: US03420C2089; ISIN: US03420C1099), a leading supplier of high-performance/ low-power 32/64-bit embedded processor IP solutions, and the driving force in taking RISC-V mainstream. Its V5 RISC-V CPU families range from tiny 32-bit cores to advanced 64-bit Out-of-Order processors with DSP, FPU, Vector, Linux, superscalar, and/or multi/many-core capabilities. By the end of 2022, the cumulative volume of Andes-Embedded™ SoCs has surpassed 12 billion. For more information, please visit https://www.andestech.com. Follow Andes on LinkedIn, Twitter, Bilibili and YouTube! 

Continue ReadingGOWIN Semiconductor & Andes Technology Corp. Announce The First RISC-V CPU and Subsystem Ever Embedded 22nm SoC FPGA

Andes Technology and TetraMem Collaborate to Build Groundbreaking AI Accelerator Chip with Analog In-Memory Computing

San Jose, CA – Aug 10, 2023 – Andes Technology, a leading supplier of high-efficiency, low-power 32/64-bit RISC-V processor cores and Founding Premier member of RISC-V International, and TetraMem Inc, a pioneer in analog memristor technology and in-memory computing, are proud to announce a strategic partnership aimed at delivering a fast, highly efficient, AI inference chip that will revolutionize the landscape of artificial intelligence and edge computing.

The convergence of AI and edge computing has become a driving force behind the advancement of numerous industries, including autonomous vehicles, smart cities, healthcare, cybersecurity, and entertainment. Recognizing the immense potential of this market, TetraMem has licensed the powerful Andes RISC-V NX27V vector CPU, combined with ACE (Andes Custom ExtensionTM) to create a cutting-edge solution that addresses the challenges of AI processing in power-constrained environments.

The centerpiece of this collaboration is the fusion of Andes’ high-performance RISC-V Vector CPU with TetraMem’s revolutionary compute memristor – an analog RRAM – in-memory computing architecture through ACE to enable tight coupling for the best performance. This unprecedented combination amplifies the strengths of both companies, resulting in blazingly fast, energy-efficient AI inference that surpasses the limitations of traditional computing approaches –  transcending “memory wall” and “end of Moore’s Law” constraints.

Features of the AI Accelerator Chip:
1. RISC-V Vector CPU Excellence: Andes RISC-V Vector CPU cores are known for their exceptional performance, efficiency, and configurability, making them ideal for a wide range of AI and edge computing applications. The addition of Andes powerful vector processor brings unparalleled performance capabilities to the accelerator chip.

2. Analog In-Memory Computing Prowess: TetraMem’s unique, analog in-memory computing technology empowers the chip with massively parallel VMM computation without data movement, mitigating the energy overhead of conventional architectures as confirmed in TetraMem’s first commercially manufactured demonstration chip.

3. Energy-Efficient AI Acceleration: The joint effort aims to create a chip that is not only powerful but improves energy-efficient by at least an order of magnitude. By optimizing computations and eliminating transfer of weight data, the planned chip will significantly extend the battery life of edge devices and impose a near-zero impact on thermal budgets.

4. Flexible and Scalable: The AI accelerator chip will be designed from 22nm and beyond, to 7nm and below in the future, with versatility and scalability in mind for easy integration into various AI-powered products and applications. This adaptability ensures broad industry applicability. The TetraMem founding team has demonstrated scalability of the compute memristor to 2nm and below, ensuring a roadmap to future-proof solutions.

Mr. Frankwell Lin, Chairman and CEO of Andes Technology, expressed his enthusiasm for the partnership, saying, “Our collaboration with TetraMem represents a significant milestone in the advancement of AI accelerators. By combining Andes’ world-class RISC-V vector processing technology with TetraMem’s groundbreaking analog in-memory computing, we are poised to deliver a revolutionary solution that will empower the next generation of AI applications.”

Dr. Glenn Ning Ge, CEO of TetraMem Inc,, echoed this sentiment, stating, “TetraMem’s analog-RRAM-based in-memory computing technology changes the physics of how AI computations are performed, launching a new era in computing. Working hand in hand with Andes, we are confident that our joint AI accelerator chip will set a new standard for AI processing in terms of speed and energy efficiency.”

Tetramem anticipates unveiling the AI accelerator chip and making engineering samples and development kits for the new 22nm “TetraMem MX Series” chip available to the public by the second half of 2024. The partnership between Andes and TetraMem signifies a major leap forward in the field of AI hardware, promising to unlock unprecedented possibilities for AI innovations.

For more information about Andes Technology and TetraMem Technologies, please visit their respective websites at www.andestech.com and www.tetramem.com.


About Andes Technology

Eighteen years in business and a Founding Premier member of RISC-V International, Andes is a publicly-listed company (TWSE: 6533; SIN: US03420C2089; ISIN: US03420C1099) and a leading supplier of high-performance/low-power 32/64-bit embedded processor IP solutions, and the driving force in taking RISC-V mainstream. Its V5 RISC-V CPU families range from tiny 32-bit cores to advanced 64-bit Out-of-Order processors with DSP, FPU, Vector, Linux, superscalar, and/or multi/many-core capabilities. By the end of 2022, the cumulative volume of Andes-Embedded™ SoCs has surpassed 12 billion. For more information, please visit https://www.andestech.com. Follow Andes on LinkedIn, Twitter, Bilibili and YouTube!

About TetraMem Inc
Founded in 2018 by a team of world-class experts, TetraMem is poised to deliver the industry’s most disruptive in-memory computing (IMC) technology for edge applications. The TetraMem team brings together complementary skill sets and technological know-how with 34 patents granted to date spanning materials science, device, circuit design, architecture, and application, as well as a patented six-dimension co-design methodology. TetraMem is the world’s only company to produce a high bit-density multi-level memristor-based accelerator in a commercial foundry, with the technology featured in the March 30, 2023 edition of the journal, Nature. This groundbreaking technology enables memory-based computation, eliminating weight-data movement, substantially improving the energy efficiency and performance of AI and machine learning workloads compared to digital technologies, with scalability well beyond the limits of competing analog technologies. For more information, please visit https://www.tetramem.com. Follow TetraMem on LinkedIn.

Continue ReadingAndes Technology and TetraMem Collaborate to Build Groundbreaking AI Accelerator Chip with Analog In-Memory Computing

Terapines ZCC Toolchain Fully Supports Andes RISC-V Processors

Wuhan, China – July 31, 2023 – Terapines Technology, an innovative provider of software/hardware co-design solutions announces the full support for Andes RISC-V processors lineup in the Terapines ZCC toolchain. The ZCC toolchain delivers proven performance gains across multiple end markets, including embedded systems, high-performance computing, and AI. Andes Technology Corporation (TWSE: 6533), a leading supplier of high efficiency, low-power 32/64-bit RISC-V processor cores and Founding Premier member of RISC-V International, has been instrumental in driving RISC-V into the mainstream. Recently, Terapines Technology has joined RISC-V International as a Strategic Member, enabling closer collaboration between these two companies and the overall RISC-V community.

The full support of ZCC toolchain for AndeStar™ V5 Instruction Set Architecture will allow Andes and its silicon partners to achieve higher code density and performance for MCU and SoC products built on the V5 architecture. It opens the door to optimized RISC-V implementations across a wider range of applications.

The benchmark results demonstrate the ZCC toolchain’s ability to optimize the system performance versus LLVM from AndeSight™ IDE. Based on AndesCore™ AX45 CPU, ZCC achieved a 6% boost over the baseline on CoreMark score, as well as an 18.9% performance improvement and 11.8% better code density on Embench-IoT (-O3). With -Os optimization, Embench-IoT attained a 10% code density gain and 9.1% faster performance.

On the industry-standard SPECInt2006 benchmark, ZCC delivered a 30% lower dynamic instruction count compared to open-source LLVM 16.0 on a RV64GCBV RISC-V processor. It also achieved a 13% lower dynamic instruction count on a RV64GCB RISC-V processor.

These gains showcase the potential of the ZCC toolchain to help engineers maximize efficiency and real-world speedup across a wide variety of RISC-V implementations.

Benchmark results also highlight the powerful auto-vectorization capabilities of ZCC toolchain for AI chip development. ZCC achieved up to 91x higher performance versus open-source compilers on popular computing kernel functions. In some cases, the auto-vectorized output even matched or exceeded hand-optimized assemblies in both performance and efficiency.

These exceptional auto-vectorization results mean ZCC can substantially accelerate AI chip design and lower software maintenance costs. By reducing the need for time-consuming manual optimization of computational kernels, ZCC provides a streamlined path to deploying high-throughput AI accelerators.

“Full support for AndeStar™ V5 ISA in the ZCC toolchain is just the starting point of our collaboration with Andes,” said Hualin Wu, CTO of Terapines Technology. “We look forward to deepening our partnership to further boost the performance and efficiency of Andes RISC-V processors. Beyond the toolchain, Terapines will provide Andes’ customers with access to our full suite of co-design tools and virtual prototype simulators. This will enable rapid and cost-effective design flow of competitive RISC-V chips optimized for their target applications.”

“This collaboration between Terapines and Andes to optimize RISC-V processor performance and code density will greatly benefit our mutual customers,” said Dr. Charlie Su, President and CTO of Andes Technology. “As RISC-V continues its rapid growth, expanding the ecosystem with professional tools like ZCC is crucial for ensuring customer product competitiveness. We look forward to broadening our collaboration to equip designers with the best-in-class solutions needed to maximize the potential of RISC-V.”

About Terapines
Founded in late 2019, Terapines Technology specializes in developing RISC-V software/hardware co-design toolchain. With optimized compilers and simulators as core technologies, Terapines offers products and solutions across four key areas: software/hardware co-design and co-verification, functional safety checker, DSA and embedded development, and ROS operating systems. To learn more about Terapines’ innovative RISC-V solutions, follow our WeChat official account or visit https://www.terapines.com

About Andes Technology
Eighteen years in business and a Founding Premier member of RISC-V International, Andes is a publicly-listed company (TWSE: 6533; SIN: US03420C2089; ISIN: US03420C1099) , a leading supplier of high-performance/ low-power 32/64-bit embedded processor IP solutions, and the driving force in taking RISC-V mainstream. Its V5 RISC-V CPU families range from tiny 32-bit cores to advanced 64-bit Out-of-Order processors with DSP, FPU, Vector, Linux, superscalar, with processor integrating vector processor and/or multi/many-core capabilities. By the end of 2022, the cumulative volume of Andes-Embedded™ SoCs has surpassed 12 billion. For more information, please visit https://www.andestech.com.  Follow Andes on LinkedIn , Twitter, Bilibili  and YouTube!

Continue ReadingTerapines ZCC Toolchain Fully Supports Andes RISC-V Processors

Andes Technology Unveils the Annual ANDES RISC-V CON, Scheduled for June 27th at the San Jose Airport DoubleTree Hotel

RISC-V: Redefining AI’s Future in Automotive, Data Center, Communications, and IoT

San Jose, CA — June 27, 2023 — Andes Technology Corporation (TWSE: 6533; SIN: US03420C2089; ISIN: US03420C1099), a leading supplier of high efficiency, low-power 32/64-bit RISC-V processor cores and Founding Premier member of RISC-V International, announces its annual ANDES RISC-V CON on June 27th at the San Jose Airport DoubleTree Hotel. In 2023, the reputable conference in the RISC-V field will focus on the theme of “RISC-V: Redefining AI’s Future in Automotive, Data Center, Communications, and IoT.” The event serves as a nexus for eminent experts, accomplished researchers, and prominent industry leaders to engage in insightful discussions regarding the latest breakthroughs in RISC-V, and the total number of registered attendees has exceeded 500.

The ANDES RISC-V CON offers an exceptional program featuring insightful presentations from Philipp Tomsich, Chair, RISC-V Software Committee; Sanjay Dave,  TSMC; Barna Ibrahim, Vice Chair, RISE Project; Adil Kidwai, EdgeQ; Larry Lapides, Imperas; Chuck Brokish, Green Hills; Shawn Prestridge, IAR. The event also includes informative technical panel: Open-Source Is Transforming AI And Hardware, involving key partners in the RISC-V ecosystem. The moderator is Dylan Patel, Chief Analyst, SemiAnalysis and panelists are Andrew Feldman, Cerebras; Horace He, Meta, Charlie Cheng, Polyhedron, Raja Khoduri, Stealth Startup and Jim Keller, Tenstorrent. Their discussion will focus on the future of AI and hardware through the lens of open-source.

The event will commence at 9:30 AM with a welcome address from Andes Technology‘s Chairman and CEO, Frankwell Lin. It will delve into the RISC-V trend and shed light on the significant contributions made by Andes in enabling the realization of the RISC-V community’s achievements. Furthermore, Dr. Charlie Su, President & CTO of Andes Technology will have the keynote “Firing on All Cylinders with Andes RISC-V Processors.” When RISC-V has been adopted in diverse applications from tiny MCUs, Linux-capable MPUs, 5G networking, enterprise storage to AI/ML accelerators with novel technologies such as compute-in-memory and photonics, the speech will give an overview of Andes RISC-V processor lineup and showcase examples of recently disclosed RISC-V applications powered by AndesCore™. In the afternoon session, Samuel Chiang, Deputy Director of Marketing of Andes Technology will also give a talk “Exploring Latest Andes RISC-V Products for Automotive and AIoT.” 

The exhibition held alongside the conference program will showcase an exciting range of technological advancements. Attendees will have the opportunity to explore the Tinker V, the first RISC-V Single-Board Computer (SBC) from ASUS IoT; an MPU development board from Renesas; an AI development kit with a camera module from Canaan; the IT9836 TDDI demo board from ITE; the PC802SCB 5G small cell reference design from Picocom; Bluetooth development kit from Telink incorporating Andes RISC-V CPU IP. Besides, there are also global leading companies to have booths and demos in Andes RISC-V CON, including EdgeQ, Gowin, Green Hills, IAR, Imperas, Menta, QuickLogic, Rapid Silicon, RISE, Siemens, Tetramem and TSMC.

ANDES RISC-V CON serves as an excellent platform for RISC-V enthusiasts to engage in personalized conversations with the knowledgeable experts worldwide. Running from 9:30 AM to 5:00 PM, the conference program ensures a comprehensive experience that encompasses a lunch and a delightful evening reception. After the Q&A sessions following the final presentation, lucky participants will have a chance to win one of two Meta VR headset and one of two Beats Earbuds. The conference is free of charge and is available to qualified registrants, including design engineers, engineering managers, marketing professionals, and business development personnel.

To register, click https://www.eventbrite.com/e/2023-andes-risc-v-con-silicon-valley-registration-624048886017?aff=oddtdtcreator

If you can’t attend in person, the event will be livestreamed. E-mail jonahm@andestech.com for the Livestream link.

About ANDES RISC-V CON
ANDES RISC- V CON is the annual RISC-V technology forum of Andes Technology. In 2023, the San Jose session will be held in Doubletree by Hilton Hotel on June 27. The 2023 theme is “RISC-V: Redefining AI’s Future in Automotive, Data Center, Communications, and IoT.” It will introduce the flexible RISC-V that changes the face of emerging computing and share how Andes assists the RISC-V ecosystem in implementing multiple applications of innovative technology. Three popular application areas will be focused on: AI, automotive electronics, and RISC-V’s new field, Android. Many RISC-V ecosystem partners, including TSMC, are invited to give talks and on-site demonstrations. For free registration, please see the official website of Andes RISC-V CON: https://www.andestech.com/Andes_RISC-V_CON_2023_US/

About Andes Technology

Eighteen years in business and a Founding Premier member of RISC-V International, Andes is a publicly-listed company (TWSE: 6533; SIN: US03420C2089; ISIN: US03420C1099), a leading supplier of high-performance/ low-power 32/64-bit embedded processor IP solutions, and the driving force in taking RISC-V mainstream. Andes’ fifth-generation AndeStar™ architecture adopted the RISC-V as the base. Its V5 RISC-V CPU families range from tiny 32-bit cores to advanced 64-bit Out-of-Order processors with DSP, FPU, Vector, Linux, superscalar, and/or multi/many-core capabilities. By the end of 2022, the cumulative volume of Andes-Embedded™ SoCs has surpassed 12 billion. For more information, please visit https://www.andestech.com. Follow Andes on LinkedIn, Facebook, Twitter, Bilibili and YouTube! 

Continue ReadingAndes Technology Unveils the Annual ANDES RISC-V CON, Scheduled for June 27th at the San Jose Airport DoubleTree Hotel

Andes Technology Showcases Pioneering RISC-V CPU IP Solutions at RISC-V Summit Europe

 Discover the Future of CPU Technology and the RISE project at Andes’ Exhibition Display in Booth 14

Barcelona, Spain – June 5, 2023 – Andes Technology Corporation (TWSE: 6533; SIN: US03420C2089; ISIN: US03420C1099), a leading provider of high efficiency, low-power 32/64-bit RISC-V processor cores and a Founding Premier member of RISC-V International, is pleased to announce its diamond sponsor participation in the prestigious RISC-V Summit Europe. This premier event, taking place from June 5 to 8, 2023 in Barcelona, Spain, will feature Andes as a key contributor, presenting a keynote speech, poster publication, and participation in an automotive panel discussion. Additionally, Andes will be showcasing its cutting-edge RISC-V CPU IP solutions at booth #14.

Join Dr. Charlie Su, President and CTO of Andes, as he delivers an engaging keynote titled “RISC-V is Firing on All Cylinders” on June 6 at 12:00 PM. Dr. Su will highlight the rapid adoption of RISC-V across a wide range of applications, from small microcontrollers to AI/ML accelerator systems in data centers. The keynote will provide examples of RISC-V applications and the corresponding solutions to support them and will also explore different approaches for matrix multiplication extension, enabling direct AI/ML acceleration with the RISC-V architecture. Furthermore, Dr. Charlie Su will contribute to a panel discussion on “Automotive/Embedded” on June 6 at 17:30 PM. Andes recently announced its new product line, AndesAIRE™, which offers highly efficient AI/ML solutions for edge and end-point inference. On, June 7, Warren Chen, Andes senior Technical Manager, Marketing, will give a demo presentation titled “Andes AI Runs Everywhere (AndesAIRE™) with DSP/Vector/NN Libraries and AndesClarity” in the demo theater on June 7 at 11:10 AM.

In addition, Andes will proudly showcase development boards with AndesCore-Embedded™ technology at booth #14. These boards include the Tinker V, the first RISC-V Single-Board Computer (SBC) from ASUS IoT; an MPU development board from Renesas; an AI development kit with a camera module from Canaan; the IT9836 TDDI demo board from ITE; and the PC802SCB 5G small cell reference design from Picocom.

You can learn more about the RISC-V Software Ecosystem (RISE) project on Andes booth #14. “Andes is proud to be part of the newly launched RISE Project, a new open source initiative to accelerate the development of software for RISC-V across a variety of market segments. Hosted by Linux Foundation Europe, RISE will support the global standards activities and achievements of RISC-V International,” said Dr. Charlie Su, CTO and President of Andes Technology and a Director of the RISE Governing Board. Please visit the RISE website for how to join and other information.

This event presents a valuable opportunity for RISC-V enthusiasts to engage in one-on-one discussions with Andes experts, enabling deeper exploration of RISC-V solutions. We invite you to visit booth #14 at the RISC-V Summit Europe and experience live demonstrations of our leading-edge CPU IP technology.

Details of Andes’ sessions during the RISC-V Summit Europe are as follows:

Tuesday, June 6,

  • 12:00 – 12:15 PM: Keynote “RISC-V is Firing on All Cylinders” by Dr. Charlie Su, President and CTO
  • 17:30 – 18:30 PM: Automotive/Embedded Panel by Dr. Charlie Su, President and CTO

Wednesday, June 7,

  • 11:10 – 11:30 AM: Demo Talk “Andes AI Runs Everywhere with DSP/ Vector/ NN Libraries and AndesClarity” by Warren Chen, Senior Technical Manager, Marketing

For more information, please visit the RISC-V Summit Europe website.

About Andes RISC-V CON
Andes RISC- V CON is the annual RISC-V technology forum of Andes Technology. In 2023, the San Jose session will be held in Doubletree By Hilton Hotel on June 27. The 2023 theme is “RISC-V: Redefining AI’s Future In Automotive, Data Center, Communications, And IoT”. It will introduce the flexible RISC-V that changes the face of emerging computing and share how Andes assists the RISC-V ecosystem in implementing multiple applications of innovative technology. Three popular application areas will be focused on: AI, automotive electronics, and RISC-V’s new field, Android. Many RISC-V ecosystem partners, including TSMC, are invited to give talks and on-site demonstrations. For free registration, please see the official website of Andes RISC-V CON: https://www.andestech.com/Andes_RISC-V_CON_2023_US/

About Andes Technology

Eighteen years in business and a Founding Premier member of RISC-V International, Andes is a publicly-listed company (TWSE: 6533; SIN: US03420C2089; ISIN: US03420C1099), a leading supplier of high-performance/ low-power 32/64-bit embedded processor IP solutions, and the driving force in taking RISC-V mainstream. Andes’ fifth-generation AndeStar™ architecture adopted the RISC-V as the base. Its V5 RISC-V CPU families range from tiny 32-bit cores to advanced 64-bit Out-of-Order processors with DSP, FPU, Vector, Linux, superscalar, and/or multi/many-core capabilities. By the end of 2022, the cumulative volume of Andes-Embedded™ SoCs has surpassed 12 billion. For more information, please visit https://www.andestech.com. Follow Andes on LinkedIn、Facebook、Weibo、Twitter、Bilibili and YouTube! 


Continue ReadingAndes Technology Showcases Pioneering RISC-V CPU IP Solutions at RISC-V Summit Europe

AndeSentry™ Collaborative Framework Enables Comprehensive RISC-V Security Solutions

Hsinchu, Taiwan — May 30, 2023 — Andes Technology Corporation (TWSE: 6533), a Founding and Premier member of RISC-V International and a leading provider of high-performance, low-power 32/64-bit RISC-V processors, has established AndeSentry™ as a collaborative framework through which companies within the RISC-V ecosystem can work together to enhance RISC-V solutions security against a wide range of threats, including both cyber and physical attacks.

As embedded, automotive, and IoT markets continue to expand, device and data security have become critical priorities for both consumers and governments. Increasingly attackers will try to hack the systems with various kinds of methods like side-channel attacks, fault injection attacks, physical attacks, etc. To prevent information leakage and system misuse due to attacks, all embedded systems and IoT devices must address security aspects in their designs. AndeSentry™ offers a comprehensive portfolio of solutions to help companies developing RISC-V based solutions achieve their security and business goals.

Addressing security concerns with a single solution can be challenging. To overcome the issue, the AndeSentry™ Collaborative Framework integrates Andes’ and its partners’ security solutions within the RISC-V ecosystem to provide a range of security solutions that cover every aspect of security requirements. These solutions include isolated execution, application integrity, RoT, cryptography IPs, secure elements, secure boot, secure debug, secure monitors for TEE, and continue to expand. They are suitable for commercial use and can enable users to meet the requirements to comply with international security standards or to pass security certifications for different applications like IoT, consumer, and automotive. Moreover, some of the solutions have pre-integrated demos and are ready for evaluation to shorten the development cycle.

“We are excited to announce that AndeSentry™ is providing a collaborative framework enabling different companies within the RISC-V ecosystem to work together to provide comprehensive security solutions for RISC-V SoCs targeting embedded and IoT systems,” said Charlie Su, President and CTO of Andes Technology. “Hex-Five, PUFsecurity, Rambus, Secure-IC, TrustKernel, Zaya, and others have joined the AndeSentry™ program. We welcome other security solution providers to join us in helping chipmakers secure their IoT SoCs.”


About Andes Technology
Eighteen years in business and a Founding Premier member of RISC-V International, Andes is a publicly-listed company (TWSE: 6533; SIN: US03420C2089; ISIN: US03420C1099), a leading supplier of high-performance/ low-power 32/64-bit embedded processor IP solutions, and the driving force in taking RISC-V mainstream. Andes’ fifth-generation AndeStar™ architecture adopted the RISC-V as the base. Its V5 RISC-V CPU families range from tiny 32-bit cores to advanced 64-bit Out-of-Order processors with DSP, FPU, Vector, Linux, superscalar, and/or multi/many-core capabilities. By the end of 2022, the cumulative volume of Andes-Embedded™ SoCs has surpassed 12 billion. For more information, please visit https://www.andestech.com. Follow Andes on LinkedIn, Facebook, Twitter, Bilibili and YouTube! 

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Andes Technology Announces the New Product Line, AndesAIRE™, Ultimately Efficient AI/ML Solutions for Edge and End-Point Inference

HSINCHU, TAIWAN – May 15, 2023 – Andes Technology (TWSE:6533), a leading supplier of high-efficiency, low-power 32/64-bit RISC-V processor cores and Founding Premier member of RISC-V International, today announced the launch of new product line, AndesAIRE™ or Andes AI Runs Everywhere, ultimately efficient solutions designed for edge and end-point inference, including the first generation of AI/ML hardware accelerator intellectual property (IP), the AndesAIRE™ AnDLA™ I350 (Andes Deep Learning Accelerator), and the neural network software tools and runtimes, the AndesAIRE™ NN SDK.

With the explosive growth of AI/ML applications, there is a critical need for high performance-efficient deep learning solutions that can operate at the edge and end-point, where the strict power and energy constraints make it difficult to only rely on CPU architecture. The AnDLA™ I350 is specifically designed to address this challenge by delivering industry-leading efficiency, low power, and small area, making it ideal for use in a wide range of edge inference applications, from smart IoT devices and smart cameras to smart home appliances and robotics.

The AndesAIRE™ AnDLA™ I350 is built on top of Andes strength on compute acceleration from the proven CPU technologies and experiences accumulated over the past 18 years, providing a high performance-efficient platform for AI/ML acceleration. It supports popular deep learning frameworks, such as TensorFlow Lite, PyTorch, and ONNX, and performs versatile neural network operations such as convolution, fully-connect, element-wise, activation, pooling, channel padding, upsample, concatenation, etc., in the int8 data type. It also features an internal Direct Memory Access (DMA) and local memory, utilizing the best computing power of the hardware engines. Operation fusion techniques are also adopted in the AnDLA™ I350 to perform most common operator sequences more efficiently. The key configurable parameters of AnDLA™ I350 include the MAC number from 32 to 4096, and SRAM size from 16KB to 4MB, and provide flexible computing power from 64 GOPS to 8 TOPS (at 1 GHz) for a wide range of applications.

The AndesAIRE™ NN SDK is a comprehensive set of software tools and runtimes for end-to-end development and deployment. It includes the following components: 

  • AndesAIRE™ NNPilot™: a neural network optimization tool suite
  •  AndesAIRE™ TFLM for AnDLA™: an AnDLA™-optimized inference framework running on a host based on TensorFlow Lite for Microcontrollers
  •  AnDLA™ driver and runtime

The NNPilot™ can automatically analyze input NN models, apply model pruning and quantization, and generate AnDLA™ executable based on its configuration to perform inference together with the TFLM framework. The NNPilot™ also generates sample host C code to invoke the AnDLA™ driver in the bare metal environment.

To address the evolving and rapidly advancing AI technologies, Andes’ vision is an extensible AI subsystem, which seamlessly integrates AndesAIRE™ AnDLA™, AndesCore™ RISC-V CPU, and Andes Custom Extension™ (ACE). In such a subsystem, most structural and time-consuming parts of the AI workloads can be computed efficiently in the AnDLA™ while less structural computations such as non-linear functions can be offloaded to the powerful and flexible RISC-V CPUs with DSP/SIMD or Vector extensions. The ACE plays a key role for efficient data movement between the CPU and the AnDLA™ to reduce significant memory bandwidth and power consumption while increasing hardware utilization. The ACE can facilitate even faster processing by generating customized instructions for domain-specific applications, such as data pre- or post-processing. In addition to the extensibilities from hardware IP’s, Andes commits to continuous advancement of AndesAIRE™ NN SDK and AndesAIRE™ NN Library for the mass-production SoCs to adopt the future AI algorithms. Andes had added more than one hundred compute library APIs yearly since 2021, and we will keep optimizing and adding new functions into NN SDK and NN library in the future.

“Andes Technology is thrilled to introduce our new product line for AI/ML solutions, the AndesAIRE™ AnDLA™ I350 and the AndesAIRE™ NN SDK, an exceptional performance-efficient hardware and an end-to-end software solution for edge and end-point inference,” said Dr. Charlie Su, CTO and President of Andes Technology. “With the AndesAIRE™, we are empowering developers and innovators to create extensible and future-proof AI/ML SoCs and applications.”

“AndesAIRE™ product line projects our vision for the AI/ML market,” said Simon TC Wang, Senior Technical Marketing Manager of Andes Technology. “By combining the advantages from RISC-V CPUs, the AnDLA™, and the ACE into an AI subsystem, the performance, power consumption, and area can be well-balanced for customers to deliver competitive solutions. Furthermore, the flexibility is guaranteed by RISC-V CPUs and NN software stack, and the extensibility is affluent for customers to differentiate their unique value for target AI/ML applications.”

The AndesAIRE™ AnDLA™ I350 and the AndesAIRE™ NN SDK are available for licensing now in an early-adopter program. For more information, please visit the Andes Technology website at “http://www.andestech.com/en/products-solutions/andesaire-ai/.”

About ANDES RISC-V CON
ANDES RISC- V CON is the annual RISC-V technology forum of Andes Technology. In 2023, the San Jose session will be held in Doubletree by Hilton Hotel on June 27. The 2023 theme is “RISC-V: Redefining AI’s Future in Automotive, Data Center, Communications, and IoT”. It will introduce the flexible RISC-V that changes the face of emerging computing and share how Andes assists the RISC-V ecosystem in implementing multiple applications of innovative technology. Three popular application areas will be focused on: AI, automotive electronics, and RISC-V’s new field, Android. Many RISC-V ecosystem partners, including TSMC, are invited to give talks and on-site demonstrations. For free registration, please see the official website of ANDES RISC-V CON: https://www.andestech.com/Andes_RISC-V_CON_2023_US/

About Andes Technology
Eighteen years in business and a Founding Premier member of RISC-V International, Andes is a publicly-listed company (TWSE: 6533; SIN: US03420C2089; ISIN: US03420C1099) and a leading supplier of high-performance/low-power 32/64-bit embedded processor IP solutions, and the driving force in taking RISC-V mainstream. Andes’ fifth-generation AndeStar™ architecture adopted the RISC-V as the base. Its V5 RISC-V CPU families range from tiny 32-bit cores to advanced 64-bit Out-of-Order processors with DSP, FPU, Vector, Linux, superscalar, and/or multi/many-core capabilities. The annual volume of Andes-Embedded SoCs has exceeded 3 billion in 2021 and continues to rise. By the end of 2022, the cumulative volume of Andes-Embedded™ SoCs has surpassed 12 billion. For more information, please visit https://www.andestech.com. Follow Andes on LinkedIn, Facebook, Twitter, Bilibili and YouTube!

Continue ReadingAndes Technology Announces the New Product Line, AndesAIRE™, Ultimately Efficient AI/ML Solutions for Edge and End-Point Inference

Upgrade to Solid Sands’ Latest SuperTest Version Supports Andes to Its Ambitions for Further Growth in the Automotive Sector

Amsterdam and Hsinchu – May 11, 2023 – Andes Technology, a leading supplier of high-performance/low-power 32/64-bit embedded processor IP solutions, has upgraded its version of the SuperTest Compiler Test and Validation Suite developed and supplied by Solid Sands.

Andes is a founding premier member of RISC-V International and the driving force in taking RISC-V mainstream. Solid Sands, the world-leading provider of testing and qualification technology for compilers and libraries, joined the RISC-V community as a Strategic Member at the end of 2022 and provided Andes with SuperTest Vermeer Update #3 to enable the company to realise its ambitious growth plans in the automotive industry.

Because C++ is capable of satisfying the security, functional safety and behavioural requirements of ISO 26262, it is increasingly used in the automotive sector. A substantial number of image processing, signal processing, and machine learning algorithms used in a vehicle’s advanced driver assistance system (ADAS) are now written in C++. Underlining the strong commitment by Andes to RISC-V technology, the latest SuperTest Vermeer version was considered to be a perfect fit when operating in such a safety-critical industry.

Andes is dedicated to delivering top-notch solutions in both AndesCore™ RISC-V IPs and software development tools. In 2022, Andes made a ground-breaking announcement by unveiling the industry’s first fully compliant with ISO 26262 functional safety standards RISC-V CPU IP, AndesCore™ N25F-SE. In the second half of 2023, Andes plans to introduce its highly anticipated AndesCore™ D25F-SE with DSP extension support. Furthermore, Andes continues to optimize compilers, toolchains, and libraries, while expanding its support for DSP/Vector and NN libraries to ensure exceptional performance right out of the box with Andes RISC-V processors. Andes provides sturdy and superior compilers and toolchains by utilizing several open-source and commercial test suites like the SuperTest.

Marcel Beemster, CTO at Solid Sands, says: “Andes has a very strong foothold in the RISC-V environment and is a forerunner in the widespread use of the technology. The company’s commitment to safety-critical development per se and its ambitions in the automotive sector in particular mean that refreshing with the latest SuperTest Vermeer version is the obvious choice.”

“Andes’ cutting-edge software development tools, like AndeSight IDE, optimizing compilers and compute libraries, help accelerate the completion of highly competitive products,” said Warren Chen, Andes Senior Manager of Technical Marketing. “We appreciate the many essential benefits that SuperTest offers and it made perfect sense for us – as we power forward in the highly demanding and exacting automotive sector – to refresh our SuperTest with the latest Vermeer version.”

About Andes Technology
 Eighteen years in business and a Founding Premier member of RISC-V International, Andes is a publicly listed company (TWSE: 6533; SIN: US03420C2089; ISIN: US03420C1099) and a leading supplier of high-performance/low-power 32/64-bit embedded processor IP solutions, and the driving force in taking RISC-V mainstream. Andes’ fifth-generation AndeStar™ architecture adopted the RISC-V as the base. Its V5 RISC-V CPU families range from tiny 32-bit cores to advanced 64-bit cores Out of Order multi-cores with DSP, FPU, Vector, Linux, superscalar, and/or multicore capabilities. By the end of 2022, the cumulative volume of Andes-Embedded™ SoCs has surpassed 12 billion. For more information, please visit https://www.andestech.com. Follow Andes
on LinkedIn, Facebook and YouTube! 

Contact:
Andes Technology Corporation
sales@andestech.com

About Solid Sands
 Founded in 2014, Solid Sands is the one-stop shop for C and C++ compiler and library testing, validation and safety services. Solid Sands offers extensive test and validation suites with a unique level of compiler and library test coverage, enabling customers to achieve the software tool quality level demanded by ISO standards. The company’s name combines sand – the world’s most abundant source of silicon – with the solidity and security expected of sector-leading testing and validation technologies. More information on the company’s products and services is available at www.solidsands.nl. You can follow Solid Sands on LinkedIn, Twitter and YouTube.

Media Contact:
Solid Sands B.V.
Marianne Damstra
marianne@solidsands.nl

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Andes Technology’s N25F RISC-V Processor Enables Superior Performance and Low Power for Phison’s X1 Enterprise SSD Controller

PHISON

Hsinchu, Taiwan – April 25, 2023 – Andes Technology (TWSE: 6533; SIN: US03420C2089; ISIN: US03420C1099), a leading supplier of high-efficiency, low-power 32/64-bit RISC-V processor cores and Founding Premier member of RISC-V International, and Phison Electronics Corp. (TPEX: 8299), a global leader in NAND flash controller and storage solutions, today announces that the AndesCore™ N25F Processor has been adopted by Phison’s award-winning PCIe Gen4x4 SSD Controller X1 (PS5020-E20) for the enterprise SSD market. The fast and compact N25F provides good balance between performance, area and power, which has made it widely adopted in SoCs demanding performance-efficient embedded controllers.

The AndesCore™ N25F is a 32-bit CPU IP core based on the AndeStar™ V5 architecture, which extends but is compatible to the RISC-V architecture. With an optimized 5-stage pipeline design, it can deliver the leading per-MHz performance with excellent energy efficiency. The N25F also has comprehensive options for its memory subsystem, including instruction and data caches, local memories with low-latency and predictable accesses, and ECC for L1 memory soft error protection. To support flexible SoC construct, the N25F system bus can be configured as 64-bit AXI, 64-bit AHB, or 32-bit AHB, and there is also a slave port for direct local memory reads/writes. These capabilities ensure both speed and security in memory accesses. In addition, the Andes Custom Extension™ (ACE) framework offers additional flexibility through customized special purpose instructions. With rich features and customized options, the N25F has been very popular in the embedded controller market.

The Phison X1 SSD platform, an U.3 PCIe 4.0 x4 NVMe SSD, is a product targeting the enterprise SSD market. Its great boost in random read IOPS is a crucial evidence for its suitability in AI training and application servers handling thousands of clients. The X1 platform offers higher speed with lower energy consumption in a cost-effective solution that eliminates performance bottlenecks, significantly improves quality of service (QoS), and delivers the highest levels of data integrity and security for critical business applications. It was also recently awarded the 2023 Taiwan Excellence Award.

“Phison has been working with Andes for almost a decade, from the previous V3 architecture to the RISC-V based V5 architecture. All AndesCore™ processors offer an extensive list of configurable options, and the ACE automation tool is very powerful in creating customized instructions that fits our exact needs.” Vincent Cheng, VP of R&D of Phison said. “We are happy to be working with Andes. Through the processor and technical support provided by Andes, it is believed that the two companies will have more possibilities for cooperation in the future.”

“The AndesCore™ N25F offers efficient performance and flexible configuration, which makes it the perfect choice for performant embedded controllers. Actually, the N25F has been the best-selling RISC-V core.” said Andes CTO and President Dr. Charlie Su. “We are grateful to work with Phison on many projects. Phison is an ideal customer who continues to develop successful products with Andes processors while providing useful feedbacks on our cores and development tools along the way. We have extended our collaboration to the superscalar D45 core and we expect more successful products from Phison based on AndesCore™.”

About Andes Technology
Eighteen years in business and a Founding Premier member of RISC-V International, Andes is a publicly-listed company (TWSE: 6533; SIN: US03420C2089; ISIN: US03420C1099) and a leading supplier of high-performance/low-power 32/64-bit embedded processor IP solutions, and the driving force in taking RISC-V mainstream. Andes’ fifth-generation AndeStar™ architecture adopted the RISC-V as the base. Its V5 RISC-V CPU families range from tiny 32-bit cores to advanced 64-bit Out-of-Order processors with DSP, FPU, Vector, Linux, superscalar, and/or multi/many-core capabilities. The annual volume of Andes-Embedded SoCs has exceeded 3 billion in 2021 and continues to rise. By the end of 2022, the cumulative volume of Andes-Embedded™ SoCs has surpassed 12 billion. For more information, please visit https://www.andestech.com. Follow Andes on LinkedIn, Facebook, Twitter, Bilibili and YouTube! 

About Phison
Phison Electronics Corp. (TPEX:8299) is a global leader in NAND Flash controller IC and storage solutions. We provide a variety of services from controller design, system integration, IP licensing to total turnkey solutions, covering applications across SSD (PCIe/SATA/PATA), eMMC, UFS, SD and USB interfaces, reaching out to consumer, industrial and enterprise markets. As an active member of industry associations, Phison is on the Board of Directors for SDA, ONFI, UFSA and a contributor for JEDEC, PCI-SIG, MIPI, NVMe and IEEE-SA.

Continue ReadingAndes Technology’s N25F RISC-V Processor Enables Superior Performance and Low Power for Phison’s X1 Enterprise SSD Controller