Ashling RiscFree™ now supports Andes Technology RISC-V CPUs

San Francisco, California – December 6, 2021 – RISC-V Summit 2021. Ashling and Andes Technology announced today that Ashling’s RiscFree™ Toolchain will be extended to support the broad range of Andes RISC-V CPU IPs including support for the AndeStar™ V5 Performance and CoDense™ ISA Extension.

RiscFree™ is Ashling’s Integrated Development Environment (IDE), Compiler and Debugger for RISC-V based development and now adds support for Andes RISC-V CPUs including the 32-bit: N22, N25F, D25F, A25, A25MP, A27, A27L2, N45, D45, A45 & A45MP and the 64-bit: NX25F, AX25, AX25MP, NX27V, AX27, AX27L2, NX45, AX45 & AX45MP.
“Ashling’s RiscFree™ with its Different Cores, One Solution feature set now brings the power of heterogeneous, multi-core debugging to Andes RISC-V CPU users allowing a single instance of RiscFree™ to debug any number of heterogeneous and homogeneous cores” said Hugh O’Keeffe, Managing Director of Ashling.

“We are delighted to have Ashling RiscFree™ support Andes RISC-V CPU cores and offer an additional choice for our customers, particularly those working on heterogeneous SoC designs utilizing AndesCore™ V5 RISC-V processors with increased performance and reduced code size” said Dr. Charlie Su, Andes Technology President and CTO.
For more information on Ashling’s RiscFree™ see: https://www.ashling.com/ashling-riscv/ and for details on Andes RISC-V CPU cores see: http://www.andestech.com/en/products-solutions/andescore-processors/.

Ashling_Andes

About Ashling
Ashling have been a leading provider of Embedded Development Tools & Services since 1982 with design centres in Limerick Ireland and Chennai India and sales and support offices in Europe, Asia Pacific, the Middle East and America. We have over thirty years’ experience in developing tools for embedded systems engineers including high-speed Debug and Trace Probes supporting a broad range of MCUs, SoCs and Soft (FPGA) based designs. Our software tools include IDEs, Debuggers, Compilers and Simulators and we support all the main embedded architectures including ARC, Arm, MIPS, Power Architecture and RISC-V through our RiscFree™ platform. We have a particular focus on RISC-V and are the first company to bring tools to the market supporting heterogenous debug of RISC-V cores along with cores from other vendors. Visit www.ashling.com for more details.
Contact Nadim Shehayed: nadim@ashling.com

About Andes Technology
Sixteen years in business and a Founding Premier member of RISC-V International, Andes is a leading supplier of high-performance/low-power 32/64-bit embedded processor IP solutions, and the driving force in taking RISC-V mainstream. Andes’ fifth-generation AndeStar™ architecture adopted the RISC-V as the base. Its V5 RISC-V CPU families range from tiny 32-bit cores to advanced 64-bit cores with DSP, FPU, Vector, Linux, superscalar, and/or multicore capabilities. The annual volume of Andes-Embedded SoCs has exceeded 2 billion since 2020 and continues to rise. At the end of Q3 2021, the cumulative volume of Andes-Embedded™ SoCs has reached 9 billion. For more information, please visit https://www.andestech.com. Follow Andes on LinkedIn, Twitter, Facebook, and YouTube! 
Contact Hsiao-Ling Lin: hllin@andestech.com 

About RISC-V
The RISC-V open architecture ISA is under the governance of the RISC-V International. Visit https://riscv.org for more details

Continue ReadingAshling RiscFree™ now supports Andes Technology RISC-V CPUs

Codeplay Software partners with Andes Technology to achieve Software First SoC Design for AI-based applications using RISC-V Vector Processors

Codeplay’s Acoran Software Platform adds support for AndesCore™ NX27V.

San Francisco, California – December 6, 2021 – Codeplay Software®, the industry leader and pioneer in Open-Standard software tools and services for artificial intelligence, machine-learning, and high-performance computing announced support for Andes Technology Corporation’s AndesCore™ NX27V IP. Andes Technology is a leader in high-performance / low-power IP and a founding premier member of RISC-V International. The NX27V is an RV64GC vector processor supporting the RISC-V Vector specification with up to 512-bit VLEN and SIMD width (or DLEN). It allows SoC designers to create next-generation compute-acceleration solutions that leverage AI, ML, and HPC in both the edge and the cloud. Initially, Codeplay will deliver support through the AndesCore performance simulator that provides near cycle accurate information. This will enable customers to implement a software-first strategy and then move to specific SoC architecture based on the NX27V.
Compute-accelerated solutions need a new programming model to leverage all the capabilities of the processing power available. Incorporating one or more vector processor cores, SoC developers and designers can create applications that leverage a Single-Instruction / Multi Data (SIMD) heterogeneous architecture. Artificial Intelligence and Machine Learning applications are required to process a significant amount of vector data for applications like neural networks and computer-vision algorithms seen in cloud acceleration cards, autonomous vehicles and visual recognition. A powerful vector processor like the NX27V can rapidly increase the performance of processing this data.
Coldplay’s Acoran software platform support for NX27V-based simulator and then SoC will provide a wide ecosystem of domain-specific optimized libraries for exascale and artificial intelligence. A key foundation of Acoran is SYCL, an open standard programming model that enables heterogeneous programming based on standard ISO C++.
“The NX27V has been adopted by about 10 customer SoC projects for the datacenter accelerators. All incorporate multiple instances of our vector processor in cluster-based heterogenous architecture,” said Dr. Charlie Su, President and CTO at Andes Technology. “The exciting partnership with Codeplay enables us to bring elegant programming solutions to our customers. We are at the beginning of the next wave SoCs with Domain-Specific Architecture (DSA) for applications ranging from embedded devices to datacenter accelerators that support AI and HPC. The growth potential in this area is enormous.”
“Codeplay is embracing the software-first approach to designing complex compute systems,” said Andrew Richards, CEO and founder of Codeplay Software. “This partnership with Andes will bring developers of RISC-V vector SoCs the opportunity to optimize their architecture based on real application software.”
“Collaboration is at the heart of the RISC-V ecosystem, so it’s great to see members join forces to develop innovative new approaches for the benefit of the entire community,” said Calista Redmond, CEO of RISC-V International. “Together, Andes Technology and Codeplay Software are offering a solution to allow developers and designers to leverage the best of open standards for hardware and software.”
“SYCL has been adopted by organizations building large supercomputers with a variety of GPU architectures. This partnership will help to bring open standard programming to the next generation of specialist processors implementing the RISC-V ISA, which is very exciting for hardware and software developers,” said Michael Wong, Chair of SYCL Working Group within The Khronos Group, Chair of Datacenter / Cloud Computing SIG with RISC-V International, and Distinguished Engineer at Codeplay Software.
Codeplay and Andes welcome companies looking to embrace RVV for accelerating their AI systems to evaluate the solution.

Codeplay_Andes

About Andes Technology
Sixteen years in business and a Founding Premier member of RISC-V International, Andes Technology (TWSE: 6533; SIN: US03420C2089; ISIN: US03420C1099) is a leading supplier of high-performance/low-power 32/64-bit embedded processor IP solutions, and the driving force in taking RISC-V mainstream. Andes’ fifth-generation AndeStar™ architecture adopted the RISC-V as the base. Its V5 RISC-V CPU families range from tiny 32-bit cores to advanced 64-bit cores with DSP, FPU, Vector, Linux, superscalar, and/or multicore capabilities. The annual volume of Andes-Embedded SoCs has exceeded 2 billion since 2020 and continues to rise. At the end of Q3 2021, the cumulative volume of Andes-Embedded™ SoCs has reached 9 billion. For more information, please visit https://www.andestech.com. Follow Andes on LinkedIn, Twitter, Facebook, and YouTube! 

About Codeplay Software
Codeplay Software is a world pioneer in enabling acceleration technologies used in AI, HPC and automotive. Codeplay was established in 2002 in Edinburgh, Scotland and developed some of the first tools enabling complex software to be accelerated using graphics processors. Today, most AI software is developed using graphics processors designed for video games, and more recently specialized AI and computer vision accelerators. Codeplay continues to work with global technology leaders to make the latest complex AI systems programmable using open standards based programming languages and allows application developers to quickly bring software to the market. Codeplay is also deeply involved with the definition of open standards, especially OpenCL™, SPIR™, SYCL™, and Vulkan™ through The Khronos Group, and MISRA C++ for automotive.
SYCL, SPIR, Vulkan are trademarks of the Khronos Group Inc. OpenCL and the OpenCL logo are trademarks of Apple Inc. used by permission by Khronos.

For more information, please contact:
Charles Macfarlane
Chief Business Officer
Codeplay Software
charles.macfarlane@codeplay.com
+44 7766 104856

Continue ReadingCodeplay Software partners with Andes Technology to achieve Software First SoC Design for AI-based applications using RISC-V Vector Processors

HPMicro Semiconductor Announces the Release of the HPM6000 Series of Microcontrollers with AndesCore™ Dual D45 Cores

Currently, the HPM6000 series is the world’s most powerful real-time RISC-V microcontrollers, with a clock speed up to 800 MHz, setting a new performance record by over 9000 CoreMark and 4500 DMIPS. Its Abundant Computing Power Accelerates Applications such as Industry 4.0, Smart Home Appliances, Edge Computing, and IoT.

Shanghai, China – December 02, 2021 – HPMicro Semiconductor, a leading manufacturer of high-performance embedded solutions, and Andes Technology, a leading supplier of 32/64-bit RISC-V embedded processors (TWSE: 6533; SIN: US03420C2089; ISIN: US03420C1099), today jointly released the HPM6000 series, the real-time RISC-V microcontrollers with the world’s strongest performance. The flagship product, HPM6750, adopts dual RISC-V AndesCore™ D45 cores, is equipped with innovative bus architecture, efficient level-1 caches and Local Memory, and has set a new performance record of over 9000 CoreMark and 4500 DMIPS, with a main frequency of up to 800 MHz. It provides robust computing power for edge computing and other applications.

The whole series of HPM6000 MCUs, including dual-core HPM6750, single-core HPM6450, and entry-level HPM6120, are all equipped with double-precision floating-point operations and powerful DSP extension instructions, built-in 2 MB SRAM, rich multimedia functions, motor control modules, communication interface and security encryption. The HPM6000 series can be used widely in popular applications such as industry 4.0, smart home appliances, payment terminal, edge computing, and IoT.

The D45 is a member of the AndesCore™ 45 series of Andes Technology RISC-V family. It has in-order 8-stage dual-issue superscalar architecture with optimized load and store pipeline design and advanced branch prediction. Additionally the D45 supports IEEE 754 single/double-precision floating-point unit (FPU) and RISC-V P-extension (DSP/SIMD) instruction. For instruction and data memory subsystem, all 45 series cores come with Local Memory as well as caches, which can greatly enhance the performance of SOCs with large memory such as the HPM6000 series. The D45 core is ideal for real-time applications that demand high performance and fast response time.

“HPMicro’s HPM6000 series are equipped with high-speed computing power and real-time control functions. They offer a more flexible and performance-efficient choice for the high-end MCU market.” Dr. Charlie Su, President and CTO of Andes Technology said, “With the D45 processor and the associated AndeSight™ IDE tools, customers can design software with better performance and streamlined program codes. HPMicro leads the industry by launching outstanding RISC-V embedded MCU security solutions. It shows the excellent R&D capabilities and efficient product development from the HPMicro team.”

“AndesCore™ D45 is the only RISC-V processor IP that can meet the requirements of HPMicro ultra-speed real-time computing. In certain use cases, D45 outperforms its competitors by 50%! In the meantime, Andes technical team’s excellent support is a big reason for us to tape out the HPM6000 series within 8 month of development and achieved one-silicon production. It was a very successful collaboration by our two teams,” said Jintao Zeng, CEO of HPMicro Semiconductor. “HPMicro provides developers with comprehensive developing tools, including HPM Studio, a free IDE based on the VS CODE framework, and a configuration tools with graphics interfaces. HPMicro will also release a BSD-licensed SDK, which includes low-level drivers, middleware and RTOS. All official software will be open-sourced. Our next step is to cooperate with more RISC-V community partners to build a better RISC-V ecosystem.”

Ordering/ Sample Information
HPM6750, HPM6450 series products samples and evaluation boards will be available by the end of December 2021. Please email info@hpmicro.com to order. For more information, please visit www.hpmicro.com

About HPMicro Semiconductor
HPMicro Semiconductor Co., Ltd. was located in Shanghai with wholly-owned subsidiaries in Tianjin and Wuhan. HPMicro’s mission is to build a high-performance general-purpose MCU portfolio that meets the modern-day demand for increased computing power. HPMicroers are a group of people who are very passionate about building world-class MCUs that challenge boundaries, break records, are easy to use, and have a good performance/price balance. HPMicro’s target market is industrial applications, including industrial automation, building control, robotic, motor control, digital power, smart appliance, and smart home.  

About Andes Technology
Sixteen years in business and a Founding Premier member of RISC-V International, Andes is a leading supplier of high-performance/low-power 32/64-bit embedded processor IP solutions, and the driving force in taking RISC-V mainstream. Andes’ fifth-generation AndeStar™ architecture adopted the RISC-V as the base. Its V5 RISC-V CPU families range from tiny 32-bit cores to advanced 64-bit cores with DSP, FPU, Vector, Linux, superscalar, and/or multicore capabilities. The annual volume of Andes-Embedded SoCs has exceeded 2 billion since 2020 and continues to rise. At the end of Q3 2021, the cumulative volume of Andes-Embedded™ SoCs has reached 9 billion. For more information, please visit https://www.andestech.com. Follow Andes on LinkedIn, Twitter, Facebook, and YouTube! 

Continue ReadingHPMicro Semiconductor Announces the Release of the HPM6000 Series of Microcontrollers with AndesCore™ Dual D45 Cores

Andes RISC-V Superscalar Multicore A(X)45MP and Vector Processor NX27V Upgrade Their Spec. and Performance

SAN JOSE, CA – December 02, 2021 – Andes Technology Corporation (TWSE: 6533; SIN: US03420C2089; ISIN: US03420C1099), a leading supplier of high efficiency, low-power 32/64-bit RISC-V processor cores and Founding Premier member of RISC-V International, today announces its superscalar multicore AndesCore 45MP family and the first commercial RISC-V vector processor IP, AndesCore NX27V, upgrade their spec and performance.

The 8-stage superscalar multiprocessor A(X)45MP was announced one year ago. It supports up to four cores and is equipped with DSP, single/double precision FPU (floating-point unit), and Linux-capable Memory Management Unit. Compared with the previous versions, the upgraded 32-bit A45MP and 64-bit AX45MP deliver up to 3x memory bandwidth while raising the floating-point performance by over 20% as measured by Whetstone benchmark. The latency for Level-1 Cache miss and Level-2 Cache hit is reduced by half and it leads to the outstanding 3.4 SPECint2006/GHz performance. In addition, the upgrade also includes RISC-V trace interface and debug spec.

The NX27V, supporting the RISC-V Vector Extension (RVV) spec v1.0-rc1, is upgraded with full configurations of 128-bit to 512-bit VLEN/SIMD/MEM. For vector data types, the NX27V now implements FP16 to FP64 and Int8 to Int64 as well as Andes-enhanced BF16 and Int4 for optimized AI data representations. The NX27V contains a scalar unit and an Out-of-Order Vector Processing Unit (VPU) with a dedicated interface called Streaming Port to efficiently exchange a large amount of data between NX27V registers and an external hardware engine. The NX27V comes with standard development tools and optimized RVV compute libraries. OpenCL™ with integrated LLVM compiler is available to enable parallel programming on heterogeneous architecture using multiple NX27V processors and a host processor such as the AX45MP. With the all 512-bit configuration, the NX27V can achieve over 98x speedup comparing with pure C program and 66% higher performance for MobileNet-v1 benchmark than the all 256-bit configuration. The NX27V targets the applications with large volumes of data such as AI, AR/VR, computer vision, cryptography, and multimedia.

“The 45-series families are welcomed by the market since introduced last year. They are used in diversified applications, ranging from highend MCU, video processing, WiFi 7, 5G base station, AI accelerators, to enterprise-grade storage devices. We are excited that the newly upgraded A(X)45MP with enhanced memory subsystem and optimized FPU can deliver prominent performance to address a wider range of applications. The industrial leading NX27V vector processor just got another award, the EDA & IP Product Award from EE Times (Nov. 16). It has been adopted by nearly 10 customer projects, targeting cloud accelerators with manycore architecture. In this release, NX27V provides a wider range of configurations to cover a variety of performance/area choices,” said Andes President and CTO Dr. Charlie Su. “Together with the complete software development environment and libraries support, A(X)45MP and NX27V are ready to serve more high-performance applications from the edge to the cloud.”

A(X)45MP and NX27V are available for licensing now. Please visit http://www.andestech.com/ for details or contact Andes sales at sales@andestech.com for more information.

About Andes Technology
Sixteen years in business and a Founding Premier member of RISC-V International, Andes is a leading supplier of high-performance/low-power 32/64-bit embedded processor IP solutions, and the driving force in taking RISC-V mainstream. Andes’ fifth-generation AndeStar™ architecture adopted the RISC-V as the base. Its V5 RISC-V CPU families range from tiny 32-bit cores to advanced 64-bit cores with DSP, FPU, Vector, Linux, superscalar, and/or multicore capabilities. The annual volume of Andes-Embedded SoCs has exceeded 2 billion since 2020 and continues to rise. At the end of Q3 2021, the cumulative volume of Andes-Embedded™ SoCs has reached 9 billion. For more information, please visit https://www.andestech.com. Follow Andes on LinkedIn, Twitter, Facebook, and YouTube!

Continue ReadingAndes RISC-V Superscalar Multicore A(X)45MP and Vector Processor NX27V Upgrade Their Spec. and Performance

Learn the Latest on RISC-V and Vector Processing at All Five Andes Technology’s Presentations at the 2021 RISC-V Summit

Visit Andes’ Exhibition Hall Display to View Live Demonstrations of its Leading-Edge CPU IP Technology

Hsinchu, Taiwan – November 30, 2021 – Andes Technology Corporation (TWSE: 6533; SIN: US03420C2089; ISIN: US03420C1099), a leading supplier of high efficiency, low-power 32/64-bit RISC-V processor cores and Founding Premier member of RISC-V International will contribute five presentations at the RISC-V Summit from December 6 to 8, 2021. The company will also demonstrate its latest RISC-V IP in a prominent booth in the RISC-V Summit Exhibition Hall.  

Andes President and CTO, Dr. Charlie Su, will deliver the keynote speech “Beefing Up the Datacenter Accelerators” on December 7 at 1:45 PM. On December 8 at 4:00 PM, Dr. Paul Ku, Deputy Technical Director of Architecture Div., will provide IOPMP updates in his presentation “The Protection of IOPMP.”

According to the ResearchAndMarkets report released in September this year, the global market for data center accelerators should grow from $13.5 billion in 2021 to $66.4 billion by 2026, at a compound annual growth rate (CAGR) of 37.6 percent for the period of 2021-2026. Design teams are being challenged to come out a scalable architecture with a limited power budget in a short time window. To address this, Dr. Su will identify the best-in-class, off-the-shelf processor IP for the task. His Keynote will explain how Andes’ RISC-V solutions help designers customize their designs to meet the high-performance goals, tightly couple them with hardwired engines, and integrate the customized processor compilers with their AI model compilers.

Additionally, Toolchain Group Manager, Dr. I-Wei Wu, will introduce “Performance of TVM AutoScheduler for Andes Vector Processor.” Chun-Wei Shu, Software Engineer, will discuss “Bring Multicore RISC-V and Zephyr RTOS Together.” In addition, Academia Sinica in collaboration with National Tsing Hua University, Taiwan and Andes will present “Sail Specification for RISC-V P-Extension.”

For more information, please visit the RISC-V Summit website.

About Andes Technology Corp.
Sixteen years in business and a Founding Premier member of RISC-V International, Andes is a leading supplier of high-performance/low-power 32/64-bit embedded processor IP solutions, and a main force to take RISC-V mainstream. Andes’ fifth-generation AndeStar™ architecture adopted the RISC-V as the base. Its V5 RISC-V CPU families range from tiny 32-bit cores to advanced 64-bit cores with DSP, FPU, Vector, Linux, superscalar, and/or multicore capabilities. The annual volume of Andes-Embedded SoCs has exceeded 2 billion since 2020 and continues to rise. To the end of Q3 2021, the cumulative volume of Andes-Embedded™ SoCs has reached 9 billion. For more information, please visit https://www.andestech.com. Follow Andes on LinkedIn, Twitter, Facebook, and YouTube!

Continue ReadingLearn the Latest on RISC-V and Vector Processing at All Five Andes Technology’s Presentations at the 2021 RISC-V Summit

Kneron Edge AI SoC Powered by Andes RISC-V Processor Core D25F

San Diego, CA, November 4, 2021 – Kneron Inc., the San Diego-based Edge AI solution provider, together with Andes Technology Corporation (TWSE: 6533; SIN: US03420C2089; ISIN: US03420C1099), a leading supplier of high-performance, low-power 32/64-bit RISC-V processor cores, today announced formal mass production of Kneron’s next-generation Edge AI SoC KL530, powered by Andes’ D25F processor in consideration of its efficient pipeline architecture, powerful Packed-SIMD DSP extension instructions, and IEEE754-compliant high-performance single/double precision floating RVFD extensions.

KL530 is the latest generation of heterogeneous AI chip from Kneron, with a brand new NPU architecture. It is the first of its kind in the industry to support INT4 precision and Transformer. Compared with other Edge AI chips, it has higher computing efficiency and lower power consumption. The use of heterogeneous AI chips embedded with RISC-V processors, powerful image processing capabilities and interfaces will further enable the application of Edge AI chips in ADAS, AIoT and other market.

The computing power of KL530 can reach 1 TOPS@INT 4, and the processing efficiency is up to 70% higher than that of INT 8 under the same hardware conditions. Its reconfigurable NPU design takes advantage of the high performance of the D25F RISC-V core, and supports multiple AI models such as CNN, Transformer, RNN Hybrid, etc. Its Smart ISP can optimize image quality based on AI, and powerful codec can achieve high-efficiency multimedia compression. In addition, its cold start time is less than 500ms, and average power consumption is less than 500mW.

The D25F CPU, one of the most popular cores from AndesCore™ 25-series, is equipped with RISC-V P-extension ISA draft to efficiently manipulate multiple data sets simultaneously in one instruction. Andes initiated the P-extension, chairs its Task Group in RISC-V International and leads the specification definition. D25F is accompanied with complete development tools including compiler with auto-generation of SIMD instructions based on vector data type, optimized DSP libraries, neural network libraries, and near cycle-accuracy simulator. It delivers near 9 times speedup for popular machine learning algorithms, including Tensorflow keyword spotting, CIFAR10 image classification, and P-net object detection.

“Kneron has a unique reconfigurable architecture, which can fit easily into different convolutional neural networks (CNN) without compromise, thus serves a wide variety of AI models seamlessly and accurately.” said Albert Liu, Kneron founder and CEO. “The D25F CPU core with its powerful DSP instruction set and development framework enables Kneron to explore the performance of its industry-leading AI algorithms to the fullest while keeping power consumption optimal. It is crucial to our customers, especially for those who develop products such as smart devices and Edge AI appliances. We are happy to cooperate with Andes, the leading computing expert specialized in RISC-V architecture. With Andes RISC-V core and its DSP support, Kneron is able to develop this cutting edge solution smoothly within a very short time frame. We are really proud to see KL530 in mass production now serving our customers.”

“We are glad that Kneron chose the D25F to power KL530, especially after it went through a series of comprehensive evaluations,” said Andes CEO and RISC-V International Board Director Frankwell Lin. “The D25F stands out distinctly in every aspect on key indexes such as product features, performance, core area, and power consumption. As a leading enterprise in providing Edge AI SoC solution embedded with RISC-V core, Kneron showed its efficiency to quickly launch KL530 and enter mass production. It is astonishing to learn the strong competitiveness of Kneron’s team. Thanks to the extraordinary cooperation between Kneron and Andes, we jointly achieved a complete and highly competitive solution to facilitate AI applications for a wide variety of products.”

Kneron KL530 Product Launch

Kneron KL530 online product launch conference will be held at 10:00-11:30 am, November 4th (PDT). GSA CEO Jodi Shelton, Winbond President Pei-Ming Chan, and YouTube Founder Steven Chan are invited to have talks to offer their perspective on the next-generation Edge AI. Registration information https://www.kneron.com/en/event-registration/ab29527e 

About Kneron

Kneron is a San Diego based technology company that was founded in 2015. It develops both hardware and software products, which are used in smart devices to run and power AI applications. Kneron is a single port of call for device manufacturers who want to integrate AI into their products. The products include hardware such as AI chips and software such as AI models, that device manufacturers can use in everything from autonomous cars, all the way down to a smart fridge, doorbell, or any Internet of Things device. Kneron primarily solves three main problems for smart devices running AI — security, energy and cost, thereby enabling AI everywhere and for everyone. Kneron’s solutions are reconfigurable, and will be as efficient at processing image and audio AI models in the future as they are now. It has raised over $100mn to date and is backed by Horizons Ventures, Alibaba, Qualcomm, Sequoia, and more. For further information about Kneron, please visit: http://www.kneron.com/about.php

About Andes Technology

Sixteen years in business and a Founding Premier member of RISC-V International, Andes is a leading supplier of high-performance/low-power 32/64-bit embedded processor IP solutions, and a main force to take RISC-V mainstream. Andes’ fifth-generation AndeStar™ architecture adopted the RISC-V as the base. Its V5 RISC-V CPU families range from tiny 32-bit cores to advanced 64-bit cores with DSP, FPU, Vector, Linux, superscalar, and/or multicore capabilities. The annual volume of Andes-Embedded SoCs has exceeded 2 billion since 2020 and continues to rise. To the end of 2020, the cumulative volume of Andes-Embedded™ SoCs has reached 7 billion. For more information, please visit https://www.andestech.com. Follow Andes on LinkedIn, Twitter, Facebook, and YouTube!

 

Continue ReadingKneron Edge AI SoC Powered by Andes RISC-V Processor Core D25F

Andes Technology Issues GDR to Be Listed on Luxembourg Stock Exchange for Expansion Plan

San Jose, California – October 29, 2021 – Andes Technology (TWSE: 6533; SIN: US03420C2089; ISIN: US03420C1099), a leading RISC-V CPU IP supplier, announced today that it successfully issued its overseas depositary receipts (GDR) on the Luxembourg Stock Exchange on September 13. Each newly issued overseas depositary receipts unit will represent 2 ordinary shares, and its initial market value is priced at US$31.78, which is approximately NT$440 per share. A total of 4 million units are issued, representing 8 million shares of common stock. The total amount raised overseas is approximately US$127 million (NT$3.517 billion). Andes Technology is currently the only public RISC-V CPU IP supplier, and the GDR shareholders are mainly foreign institutional investors who aim for long-term investment.

“The funding allows Andes to achieve the main goal of boosting medium-term and long-term capital investing in R&D and expanding product lines, especially high-end products, “Frankwell Lin, Chairman and CEO of Andes Technology stated. “Moreover, global investors are able to share the fast-growing RISC-V market. To meet the urgent demand for RISC-V high-end computing solutions, the funds will be mainly put into accelerating the expansion of product design centers to strengthen our existing leading RISC-V product portfolio as well as speed up the development of high value and high-end RISC-V CPU IPs and SoC software and hardware integrated solutions. In order to seize the market of profitable high-end multicore CPU IPs and boost sales momentum, Andes’ design centers in Taiwan, United States and Canada plan to recruit 200 R&D talents to develop the next-generation RISC-V products for applications including 5G, artificial intelligence/machine learning, HPC, ADAS, automotive electronics, AR /VR, blockchain, cloud computing, data center, server, Internet of Things, MCU, storage devices, security, wireless devices, and other massive and high-performance computing markets.”

Andes reports revenue growth of 72.6% (YoY) in the first half of 2021 and 63% of the revenue is contributed by RISC-V products, including standard IP licensing and customization computing business. In addition, the revenue of 2020 is nearly doubled from that of 2018 when Andes started delivering its initial RISC-V cores. According to Counterpoint Research’s latest report, as semiconductor solutions require more and more versatile IPs, pure play semiconductor IP market size will grow at 11% CAGR to $8.6 billion per year by 2025. RISC-V is growing rapidly, due to its open-source advantage, easier power consumption optimization, reliable security functions and lower political risk impact. RISC-V processors will continue to see fast adoption across multiple categories including IoT, industrial and automotive, which are the key sectors with 28%, 12% and 10% adoption respectively by 2025. These favorable factors for market expansion will benefit Andes and its customers.

“Andes provides hardware IP, but just like software companies, our R&D manpower is a knowledge-intensive production line,” Dr. Charlie Su, President and CTO of Andes Technology said. “Since established, Andes has devoted tremendous resources into R&D and focused on developing the best processor IPs to shorten customer’s time-to-market. That is the main reason why Andes has been able to report record-breaking revenue throughout the years. To keep the growth momentum going, Andes will recruit more R&D talents around the world. Based on the solid foundation, we will extend our portfolio to cover more high-value products and address the demand for high-performance computing solutions and grow along with the booming market.”

Looking ahead to the coming decade, as more and more international technology companies are embracing RISC-V and expanding their market and applications, Andes is determined to continue to drive the RISC-V momentum as the leading pure play processor IP vendor. By leveraging years of extensive experience helping customers achieve mass production of diversified products, Andes will support even more RISC-V SoC design teams to introduce new products and its revenue and profit will advance with the soaring RISC-V market.

RISC-V in 2025

About Andes Technology

Sixteen years in business and a Founding Premier member of RISC-V International, Andes is a leading supplier of high-performance/low-power 32/64-bit embedded processor IP solutions, and a main force to take RISC-V mainstream. Andes’ fifth-generation AndeStar™ architecture adopted the RISC-V as the base. Its V5 RISC-V CPU families range from tiny 32-bit cores to advanced 64-bit cores with DSP, FPU, Vector, Linux, superscalar, and/or multicore capabilities. The annual volume of Andes-Embedded SoCs has exceeded 2 billion since 2020 and continues to rise. To the end of 2020, the cumulative volume of Andes-Embedded™ SoCs has reached 7 billion. For more information, please visit https://www.andestech.com. Follow Andes on LinkedIn, Twitter, Facebook, and YouTube!

Continue ReadingAndes Technology Issues GDR to Be Listed on Luxembourg Stock Exchange for Expansion Plan

Andes Technology USA Corp. Announces Major Expansion of Its U.S. Operation

Company Announces Job Openings for San Jose Headquarters and Portland R&D Office

San Jose, California October 8, 2021 – Andes Technology USA Corp., the headquarters of North America operations of Hsinchu, Taiwan-based Andes Technology Corporation, a leading supplier of high efficiency, low-power 32/64-bit RISC-V processor cores and founding premier member of RISC-V International, today announced a major expansion of Its U.S. operation. Andes Technology USA is greatly increasing engineering headcount in both the San Jose, California headquarters and its Portland, Oregon research and development facility. Andes Technology USA is seeking engineers in the U.S. and Canada to work remotely or in the Portland or San Jose offices. Openings are available for design engineers, verification engineers, and field application engineers.

Andes Technology USA Corp. was established in 2015 as a California corporation coincident with Andes Technology Corp. joining RISC-V International. After Andes took the RISC-V instruction set architecture (ISA) as the base to form its fifth generation architecture, AndeStar™ V5 and started developing V5 processor IP’s, the U.S. operation was formed to be nearby early customer adopters of the new ISA. The U.S. subsidiary established an R&D lab shortly thereafter and began developing architectures for the high-end RISC-V processors. In under a year the investment together with the main engineering team in Taiwan yielded the first commercial RISC-V Vector processor IP which won nearly 10 projects including datacenter projects from a large OEM so far.

“Major semiconductor companies worldwide adopting the RISC-V ISA and the RISC-V International work groups rapid development of the RISC-V ISA extensions is driving demand for engineers to keep up with the fast pace of new technology development,” said Emerson Hsiao, Andes Technology USA Corp. Chief Operating Officer. “RISC-V customers like the growing number of extensions coming available as well as their ability to customize the architecture to better fit their processing requirements. Our tool Andes Custom Extensions (ACE) makes the customization process easier and less risky. To keep up with RISC-V technical developments and to serve our customers’ requests, we expect to greatly expand the size of our U.S. operation.”

Engineers interested in Andes are encouraged to view the open positions on the Andes Technology LinkedIn page.

 

About Andes Technology USA Corp.
Andes Technology USA Corp. was formed as a California corporation in 2015 in San Jose California to develop high-end CPU architectures. Emerson Hsiao, Chief Operating Officer heads the office, located in the heart of Silicon Valley in San Jose. In June 2018, the U.S. operation added its R&D facility in Portland, Oregon to attract engineers in the Pacific Northwest and Canada. To date, the U.S. operation continues to develop new high-end CPU processor architecture. Its most significant achievement is the development of the first RISC-V vector architecture based on the RISC-V International RVV specification. Andes developed the first RISC-V vector architecture based on version V0.8 of the specification and has advanced it to the latest to-be-ratified version.

About Andes Technology
Sixteen years in business and a Founding Premier member of RISC-V International, Andes is a leading supplier of high-performance/low-power 32/64-bit embedded processor IP solutions, and a main force to take RISC-V mainstream. Andes’ fifth-generation architecture AndeStar™ adopted the RISC-V as the base. Its V5 RISC-V CPU families range from tiny 32-bit cores to advanced 64-bit cores with DSP, FPU, Vector, Linux, superscalar, and/or multicore capabilities. The annual volume of Andes-Embedded SoCs has exceeded 2 billion since 2020 and continues to rise. To the end of 2020, the cumulative volume of Andes-Embedded™ SoCs has surpassed 7 billion.

About RISC-V AndesCore™
Andes Technology’s comprehensive CPU includes entry-level, mid-range, high-end, extensible and security families to address the full range of embedded electronics products, especially for connected, smart and green applications. From 2017, Andes expands its product line to RISC-V processors and provides a total solution in V5 family cores, including N22, N25F/NX25F, D25F, A25/AX25, A25MP/AX25MP, A27/AX27/NX27V, A45/D45/N45, AX45/DX45/NX45 and A45MP/AX45MP.

For more information, please visit https://www.andestech.com. Follow Andes on LinkedIn, Twitter, Facebook, and YouTube!

Contact Information
Andes Technology –  hr@andestech.com

Continue ReadingAndes Technology USA Corp. Announces Major Expansion of Its U.S. Operation

Andes Technology Corp. Brings Its Broad Family of RISC-V CPU IP to the Silicon Catalyst Semiconductor Incubator

Hsinchu, Taiwan and Silicon Valley, CA – September 8, 2021 – Andes Technology Corporation (TWSE: 6533), a leading supplier of high efficiency, low-power 32/64-bit RISC-V processor cores and Founding Premier member of RISC-V International, today announced that it has joined Silicon Catalyst’s In-Kind Partner program. Andes Technology will make available a wide range of its RISC-V processors to startups participating in the Silicon Catalyst incubator program.

These include all Andes RISC-V offerings between the smallest N22 to its multicore 5-stage pipeline 25 and 27 families with P extension, floating point, L2 cache controller and memory management unit. Incubator startups will also have access to Andes’ AE250 Pre-integrated AHB platform, AE350 Pre-integrated AXI platform, and AndeSight Eclipse-based Integrated Development Environment.

“Andes has been helping a steady stream of new design starts to incorporate our wide range of RISC-V AndesCore™ processors,” said Dr. Charlie Su, President and CTO of Andes Technology. “Silicon start-ups such as those in the Silicon Catalyst incubator program are ideal examples of the new ventures. Many have great products on papers but need the IP and tools to lift their design from the page and implement it in silicon. The Silicon Catalyst incubator and Andes provide them the perfect environment and high efficiency RISC-V CPU IPs to achieve this goal. We are delighted to be part of this endeavor.”

“We applaud Andes’ initiative in expanding the reach and visibility of the RISC-V ISA,” said Calista Redmond, CEO of RISC-V International. “As an open computing platform, the continued growth and adoption of RISC-V depends on a broad ecosystem of hardware and software tools and IP. Andes contributing its silicon-proven RISC-V IP to the Silicon Catalyst incubator will help make it easier for emerging startups to build the next generation of semiconductor applications with RISC-V.”

The mission of Silicon Catalyst is to lower the capital expenses associated with the design and fabrication of silicon-based IC’s, sensors, and MEMS devices. For over seven years, the Silicon Catalyst partner ecosystem has enabled early-stage companies to build complex silicon chips at a fraction of the typical cost. Silicon Catalyst has created a unique ecosystem to provide critical support to semiconductor hardware start-ups, including tools and services from a comprehensive network of In-Kind Partners (IKPs). The Portfolio Companies in the incubator utilize IKP tools and services including design tools, simulation software, design services, foundry PDK access and MPW runs, test program development, tester access, and banking and legal services. Additionally, the startups can tap into the world-class Silicon Catalyst network of advisors and investors.

“Adding a tier one RISC-V IP supplier such as Andes Technology; with its broad range of IP, hardware design tools, and integrated software development environment; broadens the selection of design IP and tools our incubator companies have to create with,” said Paul Pickering, Managing Partner at Silicon Catalyst. “Andes’ success with startups in the emerging 5G and AI chip markets demonstrates their understanding of nurturing new ventures building products for markets that are just beginning to field large numbers of new silicon designs. We are pleased to have them join the Silicon Catalyst incubator and look forward to seeing new designs containing their IP.”

About  Silicon Catalyst
It’s About What’s Next® – Silicon Catalyst is the world’s only incubator focused exclusively on accelerating solutions in silicon (including IP, MEMS & sensors), building a coalition of in-kind and strategic partners to dramatically reduce the cost and complexity of development. More than 400 startup companies have engaged with Silicon Catalyst since April 2015, with a total of 38 startup and early-stage companies admitted to the incubator. With a world-class network of mentors to advise startups, Silicon Catalyst is helping new semiconductor companies address the challenges in moving from idea to realization. The incubator/accelerator supplies startups with a path to design tools, silicon devices, networking, access to funding, banking and marketing acumen to successfully launch and grow their companies’ novel technology solutions. The Silicon Catalyst Angels was established in July 2019 as a separate organization to provide access to seed and Series A funding for Silicon Catalyst portfolio companies.

More information is available at www.siliconcatalyst.com and www.siliconcatalystangels.com

About Andes Technology
Sixteen years in business and a Founding Premier member of RISC-V International, Andes is a leading supplier of high-performance/low-power 32/64-bit embedded processor IP solutions, and a main force to take RISC-V mainstream. Andes’ fifth-generation architecture AndeStar™ adopted the RISC-V as the base. Its V5 RISC-V CPU families range from tiny 32-bit cores to advanced 64-bit cores with DSP, FPU, Vector, Linux, superscalar, and/or multicore capabilities. The annual volume of Andes-Embedded SoCs has exceeded 2 billion since 2020 and continues to rise. To the end of 2020, the cumulative volume of Andes-Embedded™ SoCs has surpassed 7 billion.

For more information, please visit https://www.andestech.com. Follow Andes on LinkedIn, Twitter, Facebook, and YouTube!

About RISC-V AndesCore™
Andes Technology’s comprehensive CPU includes entry-level, mid-range, high-end, extensible and security families to address the full range of embedded electronics products, especially for connected, smart and green applications. From 2017, Andes expands its product line to RISC-V processors and provides a total solution in V5 family cores, including N22, N25F/NX25F, D25F, A25/AX25, A25MP/AX25MP, A27/AX27/NX27V, A45/D45/N45, AX45/DX45/NX45 and A45MP/AX45MP.

For more information about Andes Technology products, please visit http://www.andestech.com/

Contact Information
Andes Technology – Jonah McLeod, jonahm@andestech.com
Silicon Catalyst – Richard Curtin, richard@siliconcatalyst.com

Continue ReadingAndes Technology Corp. Brings Its Broad Family of RISC-V CPU IP to the Silicon Catalyst Semiconductor Incubator

Andes Technology and Cyberon Collaborate to Provide Edge-Computing Voice Recognition Solution on DSP-capable RISC-V Processors

Press highlights:

  • Cyberon DSpotter, the voice wake-up and local command recognition solution, supports Andes RISC-V CPU families
  •  The local and offline command recognition provides users with a quick-response voice operation interface, protects personal privacy, and also reduces the development and maintenance costs of the device manufacturers.
  •  AndesCore™ D25F with DSP/SIMD P-extension instructions boosts the computing performance and efficiency for voice processing to provide competitive voice recognition and voice assistant solutions on edge devices

HSINCHU, TAIWAN – August 19, 2021 – Cyberon Corporation, a leading embedded speech solution provider, and Andes Technology (TWSE: 6533), a major supplier for high efficiency, low-power 32/64-bit RISC-V processor cores, announced their collaboration on the edge-computing voice recognition solution, Cyberon DSpotter, by exploring Andes DSP-capable RISC-V CPU cores such as the popular D25F and comprehensive software development environment to provide a cost-effective, high performance, and easy-to-deploy solution.

The development of AI technology has recently brought tremendous progress in speech recognition. In addition to voice assistant services based on cloud-computing architecture, there are growing demands for local voice recognition by edge-computing devices from the market. Locally executed offline command recognition provides users with a quick-response voice operation interface, protects personal privacy, and reduces the development and maintenance costs of the device manufacturers.

For many products that have a strong demand for voice control, such as wearable devices, home appliances, IoT devices, etc., low computing resource requirements and high recognition performance are important considerations. Therefore, Cyberon based on more than 20 years of professional experience, introduces its new generation algorithm, DSpotter, for voice wake-up and local command recognition.

Different from most solutions in the market, Cyberon’s DSpotter adopts phoneme-based acoustic model to improve customers’ product development efficiency. Developers do not need to collect a large amount of training corpus in advance. They can create the required commands by simply entering text. Based on the relevant foundation built over the past years, Cyberon has developed more than 40 global languages for DSpotter. It helps customers to introduce their products to the global market in a timely manner. Regarding the recognition performance, DSpotter has high accuracy and high noise robustness due to the strength of its acoustic model consisting of TDNN-F architecture. In addition, the algorithm has been well optimized by Cyberon to fit into general MCU platforms without using a dedicated neural network processor. In this way, manufacturers can provide products with voice interfaces through cost-effective hardware.

Furthermore, the performance of DSpotter is increased significantly by leveraging RISC-V DSP/SIMD P-extension (RVP) instructions on AndesCore™ D25F, a 32-bit RISC-V CPU core with highly optimized 5-stage pipeline. The RVP enables multiple data in integer registers to be processed in one single cycle, thus efficiently boosts the computations for voice, audio, image and signal processing. It also greatly improves performance for edge AI involving the above data types. The D25F is the first market-proven RISC-V RVP-capable processor, and has the most complete ecosystem in development tools, libraries for DSP and neural networks, and audio/voice codec.

“The AI technology of edge computing has gradually entered people’s lives,” said Alex Liou, VP of Cyberon Embedded solution BU. “Cyberon’s DSpotter algorithm helps developers to reduce development costs of voice recognition applications. We offer a convenient and easy-to-use tool to create customized commands of global languages. Developers can create various voice recognition applications efficiently to meet the strong and diverse demands of the market. The collaboration with Andes extends the application of DSpotter technology to RISC-V platforms and demonstrates excellent computing and recognition performances. It is hoped that it will bring more products with intelligent and convenient voice interface to people’s lives.”

”Intelligence is now in everyone’s daily life empowering not only by cloud computing but also by edge computing,” said Simon Wang, Technical Marketing Manager of Andes Technology, and in charge of RISC-V compute acceleration ecosystem. “Andes offers a comprehensive 32 and 64 bit RISC-V processor core series with high computation efficiency and low power consumption for general computing solutions. In addition, we provide AI solutions based on RVP, RVV and ACE instruction extensions with the support of Andes NN SDK and have been cooperating with partners to extend our solutions. We are excited to work with Cyberon to offer very competitive voice recognition and voice assistant solutions for edge devices based on the strength of AndesCore™ D25F, esp. its RVP support.”

About Cyberon Corporation
Cyberon Corporation, with its headquarter in New Taipei City, Taiwan, is a leading speech solution provider. Established in 2000, Cyberon has rich experiences in speech algorithm and application development. Its speech recognition and text-to-speech technologies have been widely adopted by IOT devices, home appliances, wearable devices, smart toys, automotive equipment, and enterprise customers. Cyberon provides a full range of voice solutions for embedded MCU/DSP, OS platforms, and server-based services, and is committed to providing users with natural and convenient human-machine voice interfaces. For more information, please visit http://www.cyberon.com.tw

About Andes Technology
Sixteen years in business and a Founding Premier member of RISC-V International, Andes is a leading supplier of high-performance/low-power 32/64-bit embedded processor IP solutions, and a main force to take RISC-V mainstream. Andes’ fifth-generation AndeStar™ architecture adopted the RISC-V as the base. Its V5 RISC-V CPU families range from tiny 32-bit cores to advanced 64-bit cores with DSP, FPU, Vector, Linux, superscalar, and/or multicore capabilities. The annual volume of Andes-Embedded SoCs has exceeded 2 billion since 2020 and continues to rise. To the end of 2020, the cumulative volume of Andes-Embedded™ SoCs has reached 7 billion. For more information, please visit https://www.andestech.com. Follow Andes on LinkedIn, Twitter, Facebook, and YouTube! 

Continue ReadingAndes Technology and Cyberon Collaborate to Provide Edge-Computing Voice Recognition Solution on DSP-capable RISC-V Processors