Andes Technology Announces over 2 Billion Shipments of Andes-Embedded SoCs in 2020

The Cumulative Shipments Reached a Remarkable 7 Billion by 2020

HSINCHU, TAIWAN – July 2, 2021– Andes Technology (TWSE: 6533), a leading supplier of high efficiency, low-power 32/64-bit RISC-V processor cores, announced a remarkable record of 2 billion annual SoC shipments containing its CPU IPs in 2020 at an annual growth rate of 33%. Since inception, the cumulative shipments surpassed 7 billion by the end of 2020. Applications of SoC in which Andes CPU IPs are embedded include audio, Bluetooth, gaming, GPS, machine learning, MCU, sensor fusion, SSD controllers, touch screen and TDDI controllers, storage device, voice recognition, wireless charger and more.

“Although the pandemic has impacted the global economy, the SoC shipments containing Andes CPU IPs still hit a record high. Most of the 2 billion shipments in 2020 are Andes processors of the third generation architecture (V3), but Andes’ RISC-V series IPs launched in 2017 have started to contribute royalties as well,” said Frankwell Lin, CEO of Andes Technology. “While the proportion of royalties from our RISC-V cores is still low, with the momentum of our RISC-V core licensing, we believe they will grow to dominate our royalties and become a significant part of our revenue in a much faster pace than our V3 processors. Also, Andes has continued to devote itself to contributing the RISC-V community by playing a leading role in the Board and Technical Steering Committee of the RISC-V International to influence RISC-V technical planning, business strategy, and ecosystem development.”

“The production quantity of SoCs embedded with Andes processors reaches nearly 5.5 million units per day. According to the latest forecast of 2021 Semico Research, the CAGR for RISC-V cores between 2020 and 2025 will reach 115%,” said Charlie Su, President and CTO of Andes Technology. “The key advantages of RISC-V are modularity, extensibility and compactness. They help drive the diversified applications of Andes’ customers, ranging from using only one core to over 1,000 cores on a single chip, including 5G, AI/machine learning, ADAS, AR/VR, blockchain, cloud computing, data center, IoT, sensing, storage, security, wireless and so on. As the leading RISC-V processor IP provider, Andes has launched a variety of RISC-V CPU cores, which are flexible with high performance efficiency and low power consumption in design. They also come with comprehensive software development environment, compute library, AI compiler support and open security framework. As Andes’ product portfolio covers a wider variety of emerging applications, we provide our customers with more options for different needs and help them build competitive solutions for specific fields.”

About Andes Technology

Sixteen years in business and a Founding Premier member of RISC-V International, Andes is a leading supplier of high-performance/low-power 32/64-bit embedded processor IP solutions, and a main force to take RISC-V mainstream. Andes’ fifth-generation AndeStar™ architecture adopted the RISC-V as the base. Its V5 RISC-V CPU families range from tiny 32-bit cores to advanced 64-bit cores with DSP, FPU, Vector, Linux, superscalar, and/or multicore capabilities. The annual volume of Andes-Embedded SoCs has exceeded 2 billion since 2020 and the cumulative volume has reached 7 billion by the end of 2020. For more information, please visit https://www.andestech.com

About RISC-V AndesCore™

Andes Technology’s comprehensive CPU includes entry-level, mid-range, high-end, extensible and security families to address the full range of embedded electronics products, especially for connected, smart and green applications. From 2017, Andes expands its product line to RISC-V processors and provides a total solution in V5 family cores, including N22, N25F/NX25F, D25F, A25/AX25, A25MP/AX25MP, A27/AX27/NX27V, A45/D45/N45 and AX45/DX45/NX45.

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IAR Systems extends development tools performance capabilities for Andes RISC-V cores

Latest version of IAR Embedded Workbench for RISC-V adds support for latest Andes RISC-V processor technology, including AndeStar™ V5 RISC-V Performance Extension

Uppsala, Sweden—June 23, 2021— IAR Systems®, the future-proof supplier of software tools and services for embedded development, presented a new version of its professional development tools for RISC-V. With the latest release, the complete development toolchain IAR Embedded Workbench® for RISC-V adds support for latest Andes RISC-V extension and devices, enabling maximized performance in RISC-V-based applications.

Through its excellent optimization technology, IAR Embedded Workbench for RISC-V helps developers ensure the application fits the required needs and optimize the utilization of on-board memory. With the support of the AndeStar™ V5 RISC-V Performance Extension, developers can use IAR Embedded Workbench to create applications with increased performance and reduced code size. The toolchain supports all Andes 32-bit V5 RISC-V cores, including the N22, N25F, D25F, A25, A27, N45, D45 and A45. The RISC-V Packed SIMD/DSP extension specification (RVP draft) and the corresponding intrinsic functions as well as Andes DSP libraries are supported.

“AndeStar V5 RISC-V architecture brings the unique and competitive value to our RISC-V customers,” said Dr. Charlie Su, Andes Technology President and CTO. “V5 offers full compatibility to the compact, modular and extensible RISC-V technology by supporting its standard instructions. In addition, it incorporates Andes-extended features already proven in 7+ billion AndeStar V3 processors, such as Performance extension and CoDense™ extension, to applications from edge to cloud. We welcome that IAR Systems provides full support to V5 processors and brings the benefits of IAR Embedded Workbench to the RISC-V community.”

IAR Embedded Workbench for RISC-V is a complete C/C++ compiler and debugger toolchain with everything embedded developers need integrated in one single IDE. To ensure code quality, the toolchain includes C-STAT® for static code analysis. C-STAT proves code alignment with industry standards like MISRA C:2012, MISRA C++:2008 and MISRA C:2004, and also detects defects, bugs, and security vulnerabilities as defined by CERT C and the Common Weakness Enumeration (CWE). For companies working with safety-critical applications, IAR Embedded Workbench for RISC-V is available in a functional safety edition certified by TÜV SÜD according to IEC 61508, ISO 26262, IEC 62304, EN 50128, EN 50657, IEC 60730, ISO 13849, IEC 62061, IEC 61511 and ISO 25119, delivering qualified tools, simplified validation and guaranteed support through the product life cycle.

More information about IAR Systems’ offering for RISC-V is available at www.iar.com/riscv.

IAR Systems Contacts

AnnaMaria Tahlén, Media Relations & Content Manager, IAR Systems
Tel: +46 18 16 78 00 Email: annamaria.tahlen@iar.com
Tora Fridholm, Chief Marketing Officer, IAR Systems
Tel: +46 18 16 78 00 Email: tora.fridholm@iar.com

About IAR Systems
IAR Systems supplies future-proof software tools and services for embedded development, enabling companies worldwide to create the products of today and the innovations of tomorrow. Since 1983, IAR Systems’ solutions have ensured quality, reliability and efficiency in the development of over one million embedded applications. The company is headquartered in Uppsala, Sweden and has sales and support offices all over the world. Since 2018, Secure Thingz, the global domain expert in device security, embedded systems, and lifecycle management, is part of IAR Systems Group AB. IAR Systems Group AB is listed on NASDAQ OMX Stockholm, Mid Cap. Learn more at www.iar.com.

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AndesBoardFarm Enables SoC Designers to Explore RISC-V Processors in Online FPGA Board Collection

HSINCHU, TAIWAN – June 9, 2021 – Andes Technology Corporation (TWSE: 6533), a leading supplier of high efficiency, low-power 32/64-bit RISC-V processor cores and founding premier member of RISC-V International, today announced “AndesBoardFarm”, a collection of on-line accessible FPGA boards and management software for SoC designers to experience the AndesCore™ RISC-V processors remotely from their local sites. By using the comprehensive AndeSight™ integrated development environment provided by Andes, designers can interactively try out their own software on Andes’ latest CPU cores over the internet to experiment on the performance test and get the results directly; at the same time, they can also explore the various hardware and software features offered by Andes. By taking advantage of the AndesBoardFarm services, the time and efforts for evaluating RISC-V processors will be greatly reduced, and designers will be able to pinpoint the best RISC-V CPU(s) for their SoCs with confidence.

“Creating a complex SoC with many RISC-V cores and developing applications to fully exploit the hardware features concurrently is a complex undertaking,” said Dr. Charlie Su, President and CTO of Andes Technology Corp. “Facing all the dynamics due to design complexity and fast changing requirements, it takes great visions to decide and secure the IPs that are most advantageous to their projects. To assist SoC design teams to determine the most suitable AndesCores from their own perspectives, Andes Technology created a collection of FPGA boards connected to a secure server complex and implemented secure management software. Customers can apply for an account and upload their program to an available board on the AndesBoardFarm site to save the efforts to work toward concluding their needs.” 

AndesBoardFarm FPGA boards accommodate all Andes RISC-V offerings embedded in reference SoC designs, including 32-bit and 64-bit processors with a single core or multi-core, and optional features such as MMU for Linux application, SIMD instructions for multimedia processing and vector extensions for AI and other complex computations with large volume of data.  For more information, please contact sales@andestech.com.

AndesBoardFarm

About Andes Technology
Andes Technology (TWSE: 6533) was established in Hsinchu Science Park in 2005. Sixteen years in business and a founding Premier member of RISC-V International, Andes is a leading supplier of high-performance/low-power 32/64-bit embedded processor IP solutions, and a main force to take RISC-V mainstream. Andes’ fifth-generation AndeStar™ architecture (V5) adopted the RISC-V as the base. Its V5 RISC-V CPU families range from tiny 32-bit cores to advanced 64-bit cores with DSP, FPU, Vector, Linux, superscalar and/or multicore capabilities. The annual volume of Andes-Embedded SoCs has exceeded 2 billion since 2020 and continues to rise. To the end of 2020, the cumulative volume of Andes-Embedded™ SoCs has surpassed 7 billion.

About RISC-V AndesCore™
Andes Technology’s comprehensive CPU includes entry-level, mid-range, high-end, extensible and security families to address the full range of embedded electronics products, especially for connected, smart and green applications. From 2017, Andes expands its product line to RISC-V processors and provides a total solution in V5 family cores, including N22, N25F/NX25F, D25F, A25/AX25, A25MP/AX25MP, A27/AX27/NX27V, A45/D45/N45 and AX45/DX45/NX45.
For more information about Andes Technology, please visit: http://www.andestech.com/

Continue ReadingAndesBoardFarm Enables SoC Designers to Explore RISC-V Processors in Online FPGA Board Collection

PUFsecurity and Andes Technology Cooperate to Integrate Crypto Coprocessor PUFiot into RISC-V AIoT Security Platform

HSINCHU, TAIWAN – June 2nd, 2021 –PUFsecurity, a security solutions IP company, and Andes Technology (TWSE: 6533), a leading RISC-V CPU IP vendor, are the first to incorporate PUFsecurity’s PUFiot crypto coprocessor with Andes Technology’s D25F CPU and its associated platform AE350. With this successful integration, PUFiot will become a part of the AndeSentry™ security framework from Andes Technology, offering a rich set of security solutions for the RISC-V ecosystem.

PUFsecurity jointly develops the security solution PUFiot with eMemory (TWSE: 3529), combining eMemory’s innovative NeoPUF, a physically unclonable function (PUF) that could be the chip fingerprint, along with the leading anti-fuse one-time programmable (OTP) memory, NeoFuse, and PUFsecurity’s root of trust and NIST CAVP-certified cryptographic engines (including symmetric/asymmetric ciphers, hashes, key wrapping, message authentication, etc.). Featuring multiple analog/digital anti-tampering designs to prevent both invasive attacks (such as those utilizing focused ion beam, FIB) and non-invasive ones (such as side-channel analysis), PUFiot provides a solid security boundary for chip protection.

Using PUF-derived chip fingerprints to internally generate key pairs and inborn IDs, PUFiot lowers the cost of supporting zero-touch deployment to meet the secure onboarding requirements of AI/IoT/5G multi-terabyte, networked devices. In other words, PUFiot can assist cloud-based application ecosystems in achieving zero-trust compliant security operations.

Andes Technology’s RISC-V D25F is a 32-bit high-performance processor core that supports single/double-precision floating-point operations, RVP P-extension (DSP/SIMD) instructions and Physical Memory Protection (PMP). The pre-integrated AE350 platform comprises AHB/AXI bus matrix, interrupt control, debug module, and commonly used peripherals such as GPIO, I2C, PWM, QSPI, UART, and WatchDog Timer. It greatly simplifies the SoC construction for customers. D25F processor with the AE350 platform have already been licensed to many customers for use in a broad range of market, including the emerging AIoT applications.

AndeSentry™ security framework enables open collaboration and brings out a variety of security solutions. Now included in AndeSentry™, PUFiot provides secure storage, root of trust, and hardware cryptographic engines. When integrated with the D25F+AE350 platform, PUFiot supports system-level security features such as secure boot/OTA (over-the-air) updates and firmware/software protection. The combined solution is ideal for the growing secured AIoT applications.

The successful partnership between Andes Technology and PUFsecurity is a significant milestone for the security IP industry, which will lead to the development of even more cost-effective hardware security solutions for the RISC-V ecosystem.

About PUFsecurity
PUFsecurity is a subsidiary of eMemory and is dedicated to innovating PUF-based security solutions. By leveraging our technical acumen and achievements, including core IPs such as NeoPUF and OTP from eMemory, PUFsecurity brings PUF-based security to the market. The latest solutions include the integrated, five-in-one hardware root-of-trust module (PUFrt) and PUF-based crypto co-processor (PUFiot). PUFsecurity offers hardware security IP solutions with superior performance and cost-efficiency in a wide range of process nodes with our proven industry expertise.
For more information please visit: http://www.pufsecurity.com

About Andes Technology
Sixteen years in business and a Founding Premier member of RISC-V International, Andes is a leading supplier of high-performance/low-power 32/64-bit embedded processor IP solutions, and a main force to take RISC-V mainstream. Andes’ fifth-generation AndeStar™ architecture adopted the RISC-V as the base. Its V5 RISC-V CPU families range from tiny 32-bit cores to advanced 64-bit cores with DSP, FPU, Vector, Linux, superscalar, and/or multicore capabilities. The annual volume of Andes-Embedded SoCs has exceeded 2 billion since 2020 and the cumulative volume has reached 7 billion.
For more information, please visit https://www.andestech.com

About RISC-V AndesCore™
Andes Technology’s comprehensive CPU includes entry-level, mid-range, high-end, extensible and security families to address the full range of embedded electronics products, especially for connected, smart and green applications. From 2017, Andes expands its product line to RISC-V processors and provides a total solution in V5 family cores, including N22, N25F/NX25F, D25F, A25/AX25, A25MP/AX25MP, A27/AX27/NX27V, A45/D45/N45 and AX45/DX45/NX45.
For more information about Andes Technology, please visit: http://www.andestech.com/

Continue ReadingPUFsecurity and Andes Technology Cooperate to Integrate Crypto Coprocessor PUFiot into RISC-V AIoT Security Platform

Andes Announces the New Upgrade of AndeSight™ IDE v5.0: a comprehensive software solution to accelerate RISC-V AI and IoT developments

Press Highlights:

  • AndeSight™ IDE v5.0 is to be released in mid-2021
  • Highlights of its features for AI and IoT applications include software solutions for RISC-V DSP/SIMD and Vector extension; Andes Neural Network (NN) Library; AndesClarity™ processor pipeline analyzer; debugging automation and scripting; multicore debugging; Linux LTS v5.4; and FreeRTOS and Zephyr

HSINCHU CITY, TAIWAN – April 23, 2021 –Andes Technology Corporation (TWSE: 6533), a leading supplier of high efficiency, low-power 32/64-bit RISC-V processor cores and Founding Premier member of RISC-V International, today announced the new upgrade of AndeSight™ IDE v5.0, which targets to accelerate RISC-V AI and IoT developments by strengthening several innovative and useful features.

AI and IoT applications are blooming everywhere. The products serving the market must not only come with good performance, high efficiency, and low power consumption to meet the constraints for computing and energy, but also need to reduce time-to-market to respond to the ever-changing market needs. AndeSight™  IDE v5.0 rolls out new functions to address those issues, and brings the ultimate runtime performance and development efficiency to users.

The Core for AI Computations: RISC-V DSP/SIMD extension (RVP), vector extensions (RVV), and the tools and runtime from AndeSight™ IDE

RVP exactly addresses the balance between low-volume data computation and power consumption. By providing the compact SIMD (Single Instruction Multiple Data) and DSP (Digital signal processing) capability, it forms a very competitive basis for the TinyML, AIoT, and signal processing applications on edge and endpoints. RVV targets high-volume data computation, no matter in the edge or cloud, it provides very scalable, efficient, and powerful compute capabilities for general AI, NN, and data processing applications.

To unlock the potential of a powerful ISA extension, a simple and straightforward programming model is critical. AndeSight™ IDE v5.0 supports toolchains for the standard-bound specification of RVP and RVV, highly-optimized DSP and Vector libraries, intrinsic functions, and sample codes to guide code optimization. A key advantage is that software developers can build applications completely in C using efficient intrinsic and optimized libraries APIs, freeing developers from writing error-prone assembly code, and matching the performance of the same applications built with hand-code assembly.

To explore the full capabilities of processors and achieve the ultimate performance, an advanced processor pipeline analyzer is needed. AndesClarity™ visualizes the performance and resource bottleneck. Stall bubbles and data dependency are shown clearly along with the instructions, the C source code, and hardware functional units.

In addition, Andes provides the “Andes NN Library” that dramatically speeds up the development of Neural Network algorithms. It achieves a 66x speedup of MobileNet-v1 with half-precision floating-point, 256-bit SIMD width, and 512-bit vector length over RISC-V baseline extension. Moreover, “TensorFlow Lite for Microcontroller” can execute all built-in NN models with Andes NN Library on development boards.

Develop Up-to-date RTOS and Linux Applications along with AndeSight™ IDE Powerful Tools

AndeSight™ IDE v5.0 supports Linux LTS (Long-Term Support) kernel v5.4, and the popular RTOS such as FreeRTOS and Zephyr. Andes Linux kernel has verified with LTP (Linux Test Project), and seamlessly booted with Fedora or Debian Linux distro on Andes development boards along with the device drivers. To provide a smaller image for embedded Linux applications, Andes also offers RISC-V 32-bit Linux kernel to run on the corresponding Andes processors. Andes FreeRTOS port has passed the “AWS Qualification Program for RTOS”, which validates the pre-integrated port on microcontroller-based boards by AWS (Amazon Web Service)1. Andes Zephyr port supports SMP (Symmetric Multi-Processing) and has been verified on Andes RISC-V multicore. Developers only need to focus on the application itself and do not need to worry about the fundamental software.

To further enhance the ultimate debugging efficiency, the versatile features of scripting and grouping are enabled by AndeSight™ IDE. AndeSight™ scripting can record the UI operations from one developer, and replay on another environment. It saves time to reproduce issues from the field. Similar to GDB Python scripts feature, users can automate and scale the debugging procedures with Python programming. “Core Grouping” is a useful feature to allow users to develop the multicore software with separate build and debug configurations, and sending debug commands to a specific set of cores at the same time.

AndeSight™ IDE v5.0 comprehensive features enriched from 16-year continuous development, including but not limited to the outstanding toolchains, highly-optimized C libraries, AndeSim™ near cycle simulator, easy-to-use profiling and analyzing tools, virtual hosting, RTOS awareness, and abundant reference codes.

“We are excited to announce that AndeSight™ IDE v5.0 is ready for release. AndeSight™ IDE v5.0 is the new milestone of our RISC-V software solutions. It is the latest Andes offering for RISC-V community, and we expect it to speed up RISC-V SoC development to a new level.” said Andes President and CTO Dr. Charlie Su. “Comprehensively optimized tools and runtime are the other sides of a coin. Processors cannot work efficiently and perform outstandingly without matching software solutions. We’ll continue to invest in our RISC-V software solutions to bring the best performance for RISC-V processor solutions to the RISC-V community.”

AndeSight™ IDE v5.0 will be available for licensing after June 2021. For more details of the AndeSight™ features, please visit Andes Webinar (http://www.andestech.com/en/webinar_en/) and register the talk “Accelerating RISC-V AI and IoT Development with Andes Software Solutions” at 10:00 AM (CEST) and 09:00 AM (PDT) in Arp 28 (Thu.).

 

About Andes Technology
Andes Technology (TWSE: 6533) was established in Hsinchu Science Park in 2005. Sixteen years in business and a founding Premier member of RISC-V International, Andes is a leading supplier of high-performance/low-power 32/64-bit embedded processor IP solutions, and a main force to take RISC-V mainstream. Andes’ fifth-generation AndeStar™ architecture adopted the RISC-V as the base. Its V5 RISC-V CPU families range from tiny 32-bit cores to advanced 64-bit cores with DSP, FPU, Vector, Linux, superscalar and/or multicore capabilities. The annual volume of Andes-Embedded SoCs has exceeded 2 billion since 2020. Up to the end of 2020, the cumulative volume of Andes-Embedded™ SoCs has reached 6 billion.

About RISC-V AndesCore™
Andes Technology’s comprehensive CPU includes entry-level, mid-range, high-end, extensible and security families to address the full range of embedded electronics products, especially for connected, smart and green applications. From 2017, Andes expands its product line to RISC-V processors and provides a total solution in V5 family cores, including N22, N25F/NX25F, D25F, A25/AX25, A25MP/AX25MP, A27/AX27/NX27V, A45/D45/N45 and AX45/DX45/NX45.

For more information about Andes Technology, please visit http://www.andestech.com/

 1: https://devices.amazonaws.com/detail/a3G0h0000077Y9QEAU/Corvette-F1-N25

Continue ReadingAndes Announces the New Upgrade of AndeSight™ IDE v5.0: a comprehensive software solution to accelerate RISC-V AI and IoT developments

Silex Insight and Andes Technology Extend Strategic Partnership to Deliver Flexible and Scalable Root-of-Trust Security IP Solution

April 13, 2021
Silex Insight, Mont-Saint-Guibert, Belgium
Andes Technology, Hsinchu City, Taiwan
  • Silex Insight and Andes Technology offer the eSecure solution as part of the AndeSentry™ security framework.
  • The eSecure IP module, including security boot, sensitive key material and asset protection, is perfect for security-sensitive applications

Silex Insight, a leading provider for flexible security IP cores, and Andes Technology Corporation (TWSE: 6533), a leading supplier of high efficiency, low-power 32/64-bit RISC-V processor cores, announce their strategic partnership to bring flexible and scalable Root-of-Trust security IP solutions integrated with RISC-V core to the industry.

Silex Insight’s advanced eSecure IP module, including security boot, sensitive key material and asset protection, is a complete solution that enables security applications to shield confidential information from untrusted applications running on a main processor. In the previous partnership, Andes Technology provided a high-efficiency and low-power RISC-V CPU core tightly integrated in the eSecure IP module to fully and robustly control the execution of security functions. The eSecure module is highly configurable and thus provides a wide-range selection of security features, which can be adapted for any application for performance, area and energy consumption. Andes RISC-V processors together with eSecure have been used in a wide variety of SoCs ranging from microcontrollers to data center servers, and for different purposes such as communication, and video applications.

Silex Insight and Andes Technology extend their partnership by offering the eSecure solution as part of the Andes security framework called AndeSentry™. With the combination of Silex Insight’s eSecure IP module and Andes’ versatile RISC-V processors, customers can authenticate and protect their solution in the field easily. Furthermore, customers can perform secure failure analysis/RMA (certificate based, set permissions levels, public key cryptography).
“We are able to deliver a one-stop-shop and ready-to-go solution to SoC makers who need advanced security and efficiency”, said Pieter Willems, VP of Global Sales and Marketing of Silex Insight. “With Andes Technology’s high efficiency and low-power RISC-V CPU core together with our eSecure Root-of-Trust turnkey solution, customers who demand high security on their devices can easily prevent hostile attacks from the outside world and at the same time perform end-to-end secure debugging”.

“Through our popular RISC-V processors, we have been engaged with a wide variety of customer applications. We observe that security is becoming fundamental now to all devices and connected services. Therefore we have gathered all our security solutions under one framework called AndeSentry™, where Silex Insight plays an important role with their top-notch performance solutions,” said Dr. Charlie Su, President and CTO of Andes Technology. “We are excited to be able to deliver configurable and efficient security turnkey solutions, including Silex Insight’s eSecure IP module platform, to chip design teams which need highly reliable protection”.

This robust secure solution, including end-to-end secure debugging, is perfect for security-sensitive applications, and now it is available from both Silex Insight and Andes Technology.

About Silex Insight
Silex Insight is a recognized market-leading independent supplier of Security IP solutions for embedded systems and custom OEM solutions for AVoIP/Video IP codec. The security platforms and solutions from Silex Insight include flexible and high-performance crypto engines which are easy to integrate and an eSecure IP module that provides a complete security solution for all platforms. For custom OEM solutions for AVoIP/Video IP codec, Silex Insight provides high-end image and video compression solutions for distributing low latency, 4K HDR video over IP. Development take place at the headquarters near Brussels, Belgium.

> For more information, please visit www.silexinsight.com or follow Silex Insight on LinkedIn.

About Andes Technology
Andes Technology (TWSE: 6533) was established in Hsinchu Science Park in 2005. Sixteen years in business and a founding Premier member of RISC-V International, Andes is a leading supplier of high-performance/low-power 32/64-bit embedded processor IP solutions, and a main force to take RISC-V mainstream. Andes’ fifth-generation AndeStar™ architecture (V5) adopted the RISC-V as the base. Its V5 RISC-V CPU families range from tiny 32-bit cores to advanced 64-bit cores with DSP, FPU, Vector, Linux, superscalar and/or multicore capabilities. The annual volume of Andes-Embedded SoCs has exceeded 2 billion since 2020 and continues to rise. To the end of 2020, the cumulative volume of Andes-Embedded™ SoCs has reached 7 billion.

> For more information, please visit www.andestech.com.

MEDIA CONTACTS:

Silex Insight:

Jon Jacobsen
Marketing Manager
E: marketing@silexinsight.com
P: +32 475 50 30 37
Web: www.silexinsight.com

Andes Technology:

Hsiao-Ling Lin
Marcom Manager
E: hllin@andestech.com
P: +886-3-572-6533 ext 644
Web: www.andestech.com

Continue ReadingSilex Insight and Andes Technology Extend Strategic Partnership to Deliver Flexible and Scalable Root-of-Trust Security IP Solution

Andes Technology and Rambus Collaborate to offer Secure Solution for MCU and IoT Applications

HSINCHU CITY, TAIWAN – February 24, 2021 – Andes Technology Corporation (TWSE: 6533), a leading supplier of high efficiency, low-power 32/64-bit RISC-V processor cores and Founding Premier member of RISC-V International, today announced a collaboration with Rambus Inc. (NASDAQ: RMBS), a provider of industry-leading chips and silicon IP making data faster and safer, to develop a complete low-power, size-optimized secure solution for Microcontrollers (MCUs) and Internet of Thing (IoT) applications.

According to Statista, the total number of connected IoT devices will grow to 21.5B units by 2025. As the IoT market has exploded, consumers and governments alike are demanding that device and data security requirements are a primary design requirement for all IoT devices. Accordingly, IoT device makers are increasingly demanding that MCUs be secure by design, offering “out of the box” security. To address these needs, Andes and Rambus are collaborating to offer a secure solution for MCUs embedded with Andes RISC-V -based CPU and Rambus Security Root of Trust. The Rambus Root of Trust securely boots the MCU, protects the device identity and offers authentication, secure debug, and other cryptographic services to the host system. All AndesCore™ RISC-V processors optimally leverage Rambus Root of Trust to offer these security services and reduce power for compute-intensive cryptographic operations.

“Today, security has been a fundamental and mandatory feature for IoT devices required by markets, consumers, and governments,” said Dr. Charlie Su, Andes Technology CTO and EVP. “To fulfill the requirements of different security levels, we are very pleased to collaborate with Rambus to provide an optimized secure solution for microcontrollers. With the integrated platform and FPGA ready solution of Rambus Root of Trust and Andes RISC-V processor IPs, SoC vendors can focus on their core value, key competitive and unique differentiation. They don’t need to worry about protecting the system against security threats.”

“As the connected device market continues to expand rapidly, the security of valuable assets and services is a primary concern for users and manufacturers alike,” said Gijs Willemse, senior director of product management, Rambus Security. “This collaboration will provide a strong and low-power security foundation for MCUs. It allows manufacturers to assure their customers that devices will function without the worry of security breaches that risk user privacy or interrupt their cloud services.”

AndesCore™ RISC-V processors, based on AndeStar™ V5 RISC-V architecture, consists a series of high efficiency and low power 32-bit/64-bit CPU core families range from the entry-level N22, mid-range 25-series, advanced 27-series to high-performance superscalar 45-series. Andes RISC-V vector processor NX27V is designed for broad market segments of today’s computation-intensive applications. Andes Custom Extension™ framework empowers customers to innovate Domain-Specific Acceleration via creating new instructions. AndesCore RISC-V processors have been used in a wide variety of SoCs ranging from microcontrollers to data center servers, and from edge to cloud applications. 

Providing a hardware-based foundation for security, Rambus offers a catalog of robust Root of Trust solutions, ranging from richly featured military-grade co-processors to highly compact state machines. With a breadth of solutions applicable from the data center to Internet of Things (IoT) devices, Rambus has a Root of Trust solution for almost every application.

About Andes Technology
Andes Technology (TWSE: 6533) was established in Hsinchu Science Park in 2005. Sixteen years in business and a founding Premier member of RISC-V International, Andes is a leading supplier of high-performance/low-power 32/64-bit embedded processor IP solutions, and a main force to take RISC-V mainstream. Andes’ fifth-generation AndeStar™ architecture adopted the RISC-V as the base. Its V5 RISC-V CPU families range from tiny 32-bit cores to advanced 64-bit cores with DSP, FPU, Vector, Linux, superscalar and/or multicore capabilities. The annual volume of Andes-Embedded SoCs has exceeded 2 billion since 2020. Up to the end of 2020, the cumulative volume of Andes-Embedded™ SoCs has reached 6 billion.

About RISC-V AndesCore™
Andes Technology’s comprehensive CPU includes entry-level, mid-range, high-end, extensible and security families to address the full range of embedded electronics products, especially for connected, smart and green applications. From 2017, Andes expands its product line to RISC-V processors and provides a total solution in V5 family cores, including N22, N25F/NX25F, D25F, A25/AX25, A25MP/AX25MP, A27/AX27/NX27V, A45/D45/N45 and AX45/DX45/NX45.

For more information about Andes Technology, please visit http://www.andestech.com/

Continue ReadingAndes Technology and Rambus Collaborate to offer Secure Solution for MCU and IoT Applications

Andes Technology Corp. Announces EdgeQ to Deliver Converged 5G and AI Silicon Platform with AndesCore™ RISC-V License for the 5G Open Radio Access Network

EdgeQ RISC-V based Highly Programmable 5G and AI Platform
Addresses a Multi-Trillion Dollar 5G Market Opportunity

Andes Technology Corporation (TWSE: 6533), a leading supplier of high efficiency, low-power 32/64-bit RISC-V processor cores and founding premier member of RISC-V International, today announced that EdgeQ, a leading innovator in 5G base station-on-a-chip, will utilize an AndesCore™ RISC-V license to deliver industry’s first fully open and programmable 5G platform with integrated AI. EdgeQ has licensed the Andes core with Andes Custom Extension™ (ACE). ACE enables EdgeQ to design, extend, and customize their own instruction sets to achieve novel performance, features, and power profiles unmet by today’s solutions for the wireless infrastructure.  

EdgeQ’s platform targets a 5G market that will enable $13.2 trillion of global economic output by 2035, according to the Omdia report “The 5G Economy“. The 5G value chain will invest an average of $235 billion annually to continually expand and strengthen the 5G technology base within network and business application infrastructure.

“We are excited and proud to have our RISC-V AndesCore incorporated into EdgeQ’s ambitious program to develop their 5G and AI silicon platform,” said Andes Technology President, Frankwell Lin. “Having been developed concurrent with the emergence of 5G and artificial intelligence, the 32-bit A25 processor with DSP/SIMD and floating point extensions was able to anticipate the unique computing requirements of these technologies. Using Andes ACE to easily extend the RISC-V ISA for custom requirements offers EdgeQ’s design teams the freedom to more precisely configure the performance, power consumption, and die area of their final silicon.” 

“EdgeQ was founded with the vision to provide an open programmable 5G platform that the industry can freely innovate and differentiate in a frictionless manner. Our clean-slate approach starts with a uniquely open RISC-V ISA based design that is deployable from the onset and easily modifiable by customers via open-source RISC-V tools,” said Hariprasad Gangadharan, Head of Silicon Engineering of EdgeQ. “We are pleased to have Andes as a technology partner whose proven RISC-V IP not only realizes our product vision, but at its heart offers a customizable instruction set ideal for innovators like us to shape the world in a disruptively innovative manner.” 

About EdgeQ
EdgeQ is a leading innovator in 5G systems-on-a-chip. The company is headquartered in Santa Clara, CA, with offices in San Diego, CA and Bangalore, India. Led by executives from Qualcomm, Intel, and Broadcom, EdgeQ is pioneering a converged connectivity and AI that is fully software-customizable and programmable. The company is backed by leading investors, including Threshold Partners, Fusion Fund and AME Cloud Ventures, among others. To learn more about EdgeQ, visit www.edgeq.io 

About Andes Technology
Fifteen years in business and a founding Premier member of RISC-V International, Andes is a leading supplier of high-performance/low-power 32/64-bit embedded processor IP solutions, and a main force to take RISC-V mainstream. Andes’ fifth generation AndeStar™ architecture adopted the RISC-V as the base. Its V5 RISC-V CPU families range from tiny 32-bit cores to advanced 64-bit cores with DSP, FPU, Vector, Linux, superscalar  and/or multicore capabilities. The annual volume of Andes-Embedded SoCs has exceeded 2 billion since 2020. For more information, please visit https://www.andestech.com

Continue ReadingAndes Technology Corp. Announces EdgeQ to Deliver Converged 5G and AI Silicon Platform with AndesCore™ RISC-V License for the 5G Open Radio Access Network

Andes Technology and Rafael Microelectronics Announce a Strategic Partnership to Provide High Power Efficiency Wireless IP Solutions for IoT Devices

HSINCHU, TAIWAN – January 14, 2021 – Andes Technology, a global leader in 32/64-bit RISC-V CPU core solutions, and Rafael Microelectronics, a leading provider for RF IP and wireless communication subsystem cores, are announcing a strategic partnership to bring a wireless IoT connectivity solution based on RISC-V cores to the industry.

Wireless subsystem IPs from Rafael Microelectronics are complete solutions that enable protocols of IoT connectivity to run on AndesCore™ ultra-compact N22 processor. Rafael Microelectronics offers Bluetooth® Low Energy version 5.0/5.1/5.2, Zigbee version 3.0 and full frequency band of sub gigahertz subsystems with radio designs targeting on various process nodes. The N22, a highly efficient and low-power 2-stage pipeline RISC-V CPU core, can work tightly with Rafael’s wireless subsystems to provide full control of MAC layer, Network layer and Application layer functions efficiently. The configurable wireless subsystem IPs also supply a wide-range selection of data link control for IoT devices.

“We are proud to deliver Bluetooth® Low Energy, ZigBee, WiSun and various communication IPs to SoC makers who need embedded connectivity solutions”, says Ted Sun, CEO at Rafael Microelectronics and he continues; “Combining Rafael’s RF and communication IP technology with Andes’ N22 RISC-V CPU core, we proudly offer customers our low-power, cost-effective and high-sensitivity radio solutions for their competitive wireless SoCs.”

“Wireless connectivity embedded in SoC becomes more essential for power and cost sensitive applications,” said Dr. Charlie Su, CTO and Executive VP of Andes Technology. “We are excited that the integration of our RISC-V processor core N22 with Rafael Microelectronics’ wireless subsystem IPs brings highly competitive IoT connectivity solutions to SoC vendors.”

These wireless subsystem solutions are perfect for IoT related applications and are available now from Rafael Microelectronics.

About Andes Technology
Fifteen years in business and a founding Premier member of RISC-V International. Andes is a leading supplier of high-performance/low-power 32/64-bit embedded processor IP solutions, and a main force to take RISC-V mainstream. Andes’ fifth-generation AndeStar™ architecture adopted the RISC-V as the base. Its V5 RISC-V CPU families range from tiny 32-bit cores to advanced 64-bit cores with DSP, FPU, Vector, Linux, dual-issue and/or multicore capabilities. The annual volume of Andes-Embedded SoCs is exceeding 2 billion since 2020, For more information, please visit www.andestech.com

About Rafael Microelectronics
Founded in 2006, Rafael Microelectronics is a recognized market-leading RF IC company with focus on TV and satellite tuners products. With its strong competence in RF technology, Rafael initiated RF IP and wireless subsystem IP business for IoT markets in 2017. The RF IP and wireless subsystem IP solutions from Rafael Microelectronics include Bluetooth® Low Energy, Dual Mode Bluetooth®, IEEE 802.15.4 radio, ZigBee, WiSun and custom RF IP development. Rafael also supports related communication firmware and test methodologies. Due to complexity of integrating RF communication function into an SoC, Rafael also offers Turn-Key service for Wireless SoC design service based on Andes cores. Rafael is a publicly traded company with headquarter located in Hsinchu, Taiwan. For more information please visit: www.rafaelmicro.com

Continue ReadingAndes Technology and Rafael Microelectronics Announce a Strategic Partnership to Provide High Power Efficiency Wireless IP Solutions for IoT Devices

Andes Technology Provides RISC-V CPU Core to SK Telecom

HSINCHU, TAIWAN – January 7, 2021 – Andes Technology Corp. today announced that its 64-bit AndesCore™ AX25 RISC-V processor has been adopted by SK Telecom (hereinafter referred to as “SKT”), Korea’s leading ICT company, for the development of artificial intelligence products.  Andes Technology is a leading supplier of RISC-V CPU cores. Its IP cores now are embedded in excess of 5-Billion SoCs covering a wide range of applications.

“We expect Andes Technology’s 64-bit AX25 based on RISC-V, armed with its high performance efficiency and rich configurations, to serve as the ideal controller solution for diverse NN applications on our high-performance AI chips,” said Chung Moo-kyoung, Project Leader of AI Accelerator at SKT. “We will continue to focus on innovating user experiences by realizing advanced AI technologies and solutions.”

“We are excited to collaborate with SKT by providing our processor AX25 to be a key component of SKT’s deep learning SoCs,”  said Andes President Frankwell Lin. “The growing intelligent devices call for SoCs with ever more complex computing capabilities. To meet the increasing demands from customers, all Andes V5 processors support RISC-V ratified spec and thus fully benefit from expanding RISC-V ecosystem; in addition, they come with extensive configurable features for embedded applications and user-friendly software development environment.” For example, Andes supports vector interrupt and unaligned access for better performance efficiency and novel features such as PowerBrake, QuickNap™ for additional power saving; StackSafe™ for stack overflow/underflow protection; and CoDense™ for additional code density enhancement on top of RISC-V C-extension.

AndesCore AX25 is equipped with RISC-V P-extension (RVP) ISA to efficiently manipulate multiple data sets simultaneously in one instruction and assist various AI computations. It is also perfect for control-oriented tasks with features such as dynamic branch prediction, instruction/data caches and local memories for low-latency accesses. ECC soft error protection is also supported. Complementing the hardware is AndeSight™, a feature-rich and intuitive integrated development environment. Furthermore, Andes Custom Extension™ (ACE) is a powerful framework to enable custom instruction design to realize domain specific acceleration with high degree of programmability within a reduced development time.

About Andes Technology
Fifteen years in business and a Founding Premier member of RISC-V International, Andes is a leading supplier of high-performance/low-power 32/64-bit embedded processor IP solutions, and a main force to take RISC-V mainstream. Andes’ fifth-generation AndeStar™ architecture adopted the RISC-V as the base. Its V5 RISC-V CPU families range from tiny 32-bit cores to advanced 64-bit cores with DSP, FPU, Vector, Linux, dual-issue and/or multicore capabilities. The annual volume of Andes-Embedded SoCs is exceeding 2 billion since 2020. For more information, please visit https://www.andestech.com.

Continue ReadingAndes Technology Provides RISC-V CPU Core to SK Telecom