Markets & Applications
AndesCore™ 32-bit CPU Cores Ideal for 8-bit CPU Replacement in Embedded Applications
From the original 8008 launched in the late 1970s to the 6502 that powered the early Apple II, to the 8088 that launched the IBM PC, and to the long-lived 8051 that powers many microcontrollers to this day, the 8-bit processor has had a long run. However, today's embedded applications are demanding more powerful 32-bit processors to handle a multitude of new computing, communications, and security requirements over long periods of time without battery recharge or energy harvesting. Examples include electronic shelf labels, smoke and CO2 detectors, lab on a chip, intrusion detection, keyless entry, and many more.
Only one 32-bit CPU architecture, the AndesCore™ series of high performance 32-bit CPU cores, among many, offers the silicon footprint of an 8-bit CPU, computation power, and energy efficiency to meet the need of these embedded applications. Each AndesCore CPU implements the backward-compatible AndeStar™ instruction set architecture (ISA), which is in its third generation (V3). Power management features not available on the older 8-bit CPUs are common in the AndeStar architecture. The AndesCore N705, for example, comes with a feature called PowerBrake that allows the CPU clock rate to be dynamically throttled. The CPU can be running at full 100% with a high processing load and then scale down to 10% when the load is lessened. In addition to the CPU, there are power savings features incorporated into the peripherals surround the CPU in the form of pre-integrated and pre-verified Platform IP AE210, something not incorporated in the earlier 8-bit processors.
Most embedded microcontrollers stored their programs in on-chip flash or ROM. As a result, adopting a CPU with higher code density leads to a lower total chip cost. A misconception is that 8-bit CPUs have more compact code size than 32-bit CPUs. AndeStar ISA's CoDense™ technology together with Andes highly optimized compiler offers the industry's leading compact code size. Take an open-source Zigbee stack as example. It requires 50 KB for 8051, but only needs less than 22 KB, a 56% reduction, for AndesCore N705.
Another feature for the AndesCore N705 is flash acceleration since embedded applications rely on flash for program storage. An 8-bit CPU fetches its program an instruction at a time from flash. An extension feature for the AndesCore N705 called FlashFetch™ holds a small number of instructions to eliminate the need to access them from flash, a power consuming operation. Depending on the CPU frequencies, running the Coremark and DMIPS benchmarks with FlashFetch can boost the score from 30 to over 100 percent.
Another AndeStar architecture capability that makes it ideal for 8-bit replacement is its extension features for physical security such as secure interrupt with hardware memory stacking, data and address scrambling, and differential power analysis protection. Secure interrupt protects the CPU states (including register file and program stack) of secure software (such as a crypto function) from the potential attack via a malicious ISR (interrupt service routine) without compromising the real-time response of harmless cooperative ISR's. Scrambling defends against attacks that target the interface between CPU and memory. Power analysis protection guards against hacking the program by observing the power use signature of the CPU. This is achieved by randomizing the execution cycles of the CPU to make it unintelligible to an attacker. The AndeStar architecture also blocks software/firmware attacks from hacking the JTAG interface.
Only the AndesCore series of high performance 32-bit CPU cores, designed in the past decade, can deliver low cost, low power consumption and high security demanded by today's emerging high volume embedded applications.