Events

2018 RISC-V Workshop in Barcelona - May 9

2018-05-07

WHO:  Andes Technology Corporation, the leading Asia-based supplier of small, low-power, high performance 32/64-bit embedded CPU cores, today announced that it will make two presentations at the 2018 RISC V Workshop in Barcelona.

WHAT:  In one presentation Chuan-Hua Chang, Senior Director of Architecture Division, Andes Technology Corporation and Richard Herveille, Managing Director, RoaLogic BV will propose an extension to RISC-V community based the DSP ISA used in Andes’ highly successful D10 and D15 processors.  In the second presentation Charlie Su, CTO and Senior VP, Andes Technology Corporation will will describe four new RISC-V IP processors with complaint floating-point and Linux support: the 64-bit NX25F and AX25, and 32-bit N25F and A25.

WHEN:  Wednesday, May 9th, 2018, Chuan-Hua Chang, Senior Director of Architecture Division, Andes Technology Corporation and Richard Herveille, Managing Director, RoaLogic BV will present at 0915. Charlie Su, CTO and Senior VP, Andes Technology Corporation will present at 1430. Click here for agenda.

WHERE: Universitat Politècnica de Catalunya, Barcelona, Campus Nord, Calle Jordi Girona, 1-3, 08034 Barcelona, Spain. To schedule a meeting e-mail info@andestech.com