2018 Andes RISC-V Con Silicon Valley - Nov 13


2018 Andes RISC-V Con Silicon Valley

RISC-V, an open instruction set architecture (ISA), has rapidly evolved into a new mainstream embedded processor technology. Andes positions itself as a professional and reliable vendor of RISC-V processors and solutions and launched several new RISC-V based products recently. Andes RISC-V CON will focus on this disruptive technology, demonstrating its benefits and identifying commercial strategies.

Come listen to speeches like "Unleashing Chip Design Barrier With RISC-V", "Comprehensive RISC-V Solutions for AIoT" and many other informative topics to help you quickly bring designs based on the open RISC-V ISA to market.

Date: November 13th (Tue.)
Time: 9:00~17:00
Venue: Hyatt Regency Santa Clara

Regiser now
Event website