General Description

Quick-Start Design Package is a complete solution that significantly reduces time to market for SoC designs. The package includes the AndesCore™ N650 CPU IP, AndeShape™ AE100 Platform IP, and AndeSight™ MCU IDE software development environment. The N650 CPU IP provides the performance-efficiency needed for entry-level SoCs. It is the best candidate to replace 8051 and other 8-bit MCUs for small-footprint, cost- and power-sensitive applications. The AE100 Platform IP provides a light-weight base structure of SoC constructed by a configurable AHB Fabric with APB Bridge as well as several essential peripheral IPs. With AE100, users can easily build a low-cost SoC with high flexibility and fast time-to-market. All the AE100 components are designed to minimize the access latency, the logic gate count, and the power consumption. By pre-integrating and pre-verifying processor, fabric, and peripherals, the package jump-starts customer's SoC projects with a solid foundation and reduces custom glue logic design teams need to create and verify.

Package Contains:

AndesCore™ N650 CPU IP

Performance
  • 1.27 DMIPS/MHz; 2.80 CoreMark/MHz
  • 16/32-bit mixable instruction format for compacting code density
  • Completion of most 32-bit operations in one cycle
  • Single-cycle capable AHB bus accesses
  • Low-latency vectored interrupt for real-time performance

Flexibility
  • Easy arrangement of preemptive interrupts
  • Stack protection hardware to help determining stack size needed, and to detect runtime overflow error
  • Processor state bus to simplify SoC design and debug
  • Fixed big or little endian support
  • Memory-mapped I/O space
  • All-C Embedded Programming

Power Management
  • Extensively clock-gated pipeline
  • Low power modes initiated by SW or SoC
  • PowerBrake technology to reduce power consumption


AndeShape™ AE100 Platform IP
IP Description
ATCAPBBRG100 AHB-to-APB bridge
ATCBUSDEC200 AHB-Lite decoder
ATCGPIO100 GPIO controller
ATCMSTMUX100 AHB-Lite master multiplexer
ATCPIT100 Programmable interval timer
ATCRAMBRG200 Low-latency RAM bridge
ATCSPI100 SPI controller
ATCUART100 UART controller
ATCWDT200 Watchdog timer


AndeSight IDE v2.1 MCU-N6
  • Eclipse-based with rich enhancement

Block Diagram

N650 Block Diagram
System Block Diagram

Feature Highlight

N650 Key Features

CPU Core
  • AndeStar V3m architecture
  • 3-stage pipeline
  • 16 32-bit general-purpose registers
  • Choice of multiplier
    • Fast (1 cycle) for performance
    • Small (17 cycles) for size
  • Hardware divider for performance
  • Direct support of up to 32 interrupts with programmable priority levels
  • Performance monitor
  • Memory-mapped I/O
  • Clock gating and logic gating to reduce power

Bus Interface
  • One AHB-Lite port
  • 16MB address space

Debug Support
  • Debug interface
    • Andes 2-wire Serial Debug Port (SDP)
  • Embedded debug module (EDM)
    • Up to 8 breakpoint/watchpoints

AE100 Key Features

  • Configurable AHB Fabric with APB Bridge
    • 24-bit address width
    • 32-bit data width
    • Supports up to 8 AHB-Lite masters
    • Supports up to 30 AHB-Lite slaves
    • Supports up to 31 APB slaves
  • Essential Peripheral IPs
    • Low-latency RAM bridge
    • SPI controller supporting memory-mapped access and DMA
    • UART controller compatible with 16C550D
    • GPIO controller supporting up to 32 I/Os
    • Programmable interval timer / PWM
    • Watchdog timer
  • Compact Reference Designs
    • Clock generation
    • Reset generation
    • System Management Unit (SMU)
  • Two Pin-configurable Bootstrap Addressing
    • 0x00_0000 and 0x80_0000

Development Tools

  • Software Tools
    • Feature-rich AndeSight GUI IDE
    • Andes BSP with demo examples
  • RTOSes
    • Both popular open-source and commercial are supported
    • Available upon requests
  • FPGA Development Boards
    • AndeShape ADP-XC7 (full-featured)
    • AndeShape Corvette F1 (Arduino-compatible)
  • Debugging Hardware
    • AndeShape AICE-MINI