AndeStar™ Architecture

AndeStar™ V3 Families

AndeStar™ is a series of patented 32-bit/64-bit RISC-style CPU architecture. Its third generation V3 instruction set includes 16-bit and 32-bit mixed-length instructions to achieve optimal system performance, code density and power efficiency. It has rich configuration features such as 16 or 32 32-bit general purpose registers, DSP instructions, Floating-Point coprocessor instructions, custom coprocessors, and security-enhanced MPU against memory tampering. V3 also has the unique Andes Custom Extension™ (ACE) framework that allows customers to define their own instructions easily and create more differentiations. Its CoDense™ instructions further compact the already very small code size. The GPR (general-purpose registers) based DSP instructions offers an efficient speedup for voice and audio applications as well as image processing. The IEEE-754 compliant Floating-Point coprocessor provides optional single precision or double-and-single precision instructions for fast floating-point computations. Its power management instructions and interface protocol simplify switching among different SoC operating modes related to power and performance. V3 architecture contains optional Memory Protection Unit (MPU) to run secure RTOS and optional Memory Management Unit (MMU) with hardware table walker for virtual memory OS’es such as Linux. It supports a shadow stack pointer register to simplify the protection of the kernel stack pointer. V3 vectored interrupt architecture with priority-based preemption, including 4 priority levels and built-in interrupt controller for up to 32 interrupt sources. All-C Embedded Programming is another major benefit enabled. Software engineers can program startup functions and ISRs (Interrupt Service Routines) in pure C language, and thereby gain higher productivity and reduce maintenance overhead. V3m/V3m+ is the subset of V3 to enable smaller and lower power AndesCore™. V3m/V3m+ instructions are carefully selected from those most commonly used in MCU applications. In addition, V3m/V3m+ also supports the priority-based preemption with built-in vector interrupt controller and All-C Embedded Programming.

Those features and configurability enable AndeStar™ V3 families to support a wide range of applications from low power compact micro-controllers to high-performance Linux-based embedded systems. The unit volume of SoC’s embedded with the V3 family processors has exceeded 2 billions in 2017.

AndeStar™ V5 Families

Andes is a founding member of the RISC-V Foundation and the first established CPU IP vendor to adopt RISC-V as the subset of its fifth generation architecture, AndeStar™ V5. The key advantages of V5 inherited from RISC-V are compact, modular and customizable, with an emerging and fast-growing ecosystem. In addition to full compatibility to RISC-V technology by supporting its standard instructions, V5 brings Andes-extended features already proven in V3 to be effective and beneficial to embedded applications. Among those features are Andes-extended instructions for performance enhancement and code size reduction as well as StackSafe™ stack protection, PowerBrake power management, and vectored Platform Level Interrupt Controller (PLIC) with priority-based preemption. V5 also comprises 64-bit architecture that has more than 4GiB address space, necessary for applications like storage, networking, artificial intelligence, argument reality and virtual reality. Andes is committed to driving the acceleration of the acceptance of the RISC-V by taking RISC-V mainstream.

The following list the key features of AndeStar™:

  • Intermixable 32-bit and 16-bit instruction sets without the need for mode switch
  • 16-bit instructions as a frequently used subset of 32-bit instructions
  • RISC-style register-based instruction set
  • 32 or 16 32-bit General Purpose Registers (GPR)
  • Upto 1024 User Special Registers (USR) for existing and extension instructions
  • Rich load/store instructions for
    • Single memory access with base address update
    • Multiple aligned and unaligned memory accesses for memory copy and stack operations
    • Data prefetch to improve data cache performance
    • Non-bus locking synchronization instructions
  • PC relative jump and PC read instructions for efficient position independent code
  • Multiply-add and multiple-sub capable of 64-bit result accumulation
  • Efficient power management through standby instruction and flexible interface signals
  • Bi-endian support
  • Optional coprocessor interface for
    • Andes-defined Floating-Point Coprocessor with efficient floating-point instructions
    • Customer coprocessor for customer-defined instruction extensions
  • Memory space management through :
    • 4-entry Non-translation cacheability and mapping table
    • Memory Protection Unit (MPU) for RTOS and bare-metal environment
    • Memory Management Unit for virtual memory OS with a choice of hardware or software page table walker
  • Memory hierarchy definition, including
    • Instruction and Data Local Memory (ILM and DLM): each occupying a relocatable part of the global address space
    • Instruction and Data Caches: the first level SW visible caches, capable of keeping contents in the global address space other than ILM/DLM

The following list the key Andes-extended features at the V5 architecture level:

Instruction extensions:

  • Memory accesses with fewer instructions
    • GP-implied load/store instructions with longer immediate
    • Calculate effective address based on data type
  • Compare register with a small constant and branch
  • Handy instructions for zero/sign-extension
  • CoDense™ instructions for code size compaction
  • Andes Custom Extension™ for DSA (Domain-Specific Architecture)
  • GPR-based efficient DSP instruction extension for both 32-bit V5 and 64-bit V5 (submitted as P extension to RISC-V)

Non-instruction extensions:

  • Instruction and Data Local Memory (ILM and DLM): each occupying a configurable part of the global address space
  • Vectored PLIC with priority-based preemption and configurations up to 1023 inputs, 256 priorities and 16 targets
  • StackSafe™ protection for stack overflow and underflow
  • Cache management control to operate on cache tag and data directly
  • PowerBrake for digitally scaling frequency
  • Performance counter with overflow interrupt and privileged-mode-specific counting features.