AndeStar™ Architecture

AndeStar™ is a patented 32-bit RISC-style CPU architecture. Its instruction set includes 16-bit and 32-bit mixed-length instructions to achieve optimal system performance, code density and power efficiency. AndeStar architecture supports rich configuration features such as 16 or 32 32-bit general purpose registers, instruction and data cache, instruction and data Local Memory, DMA, MMU, MPU, coprocessors, DSP instructions, saturation instructions, 16MiB or 4GiB address space, interrupt mechanisms, etc. It also includes handy power management instructions and interface protocol to simplify switching among different SoC operating modes related to power and performance, and a floating-point coprocessor supporting IEEE-754 compliant floating-point instructions for fast floating-point computations. These configuration features enable AndeStar to support a wide range of applications from low power compact micro-controllers to high-performance Linux-based embedded systems.

The evolution of AndeStar from V1 architecture to current V3 architecture provides great improvements in performance and code size. V2 ISA supports 16-bit SP-implied load/store and 32-bit GP-implied load/store; the enlarged immediate offset constants in these instructions allow the compiler to produce smaller code size due to efficient accesses to stack or global variables for most programs. In addition to those in the V2 architecture, V3 adds 38 new instructions with rich semantics for further code size reduction and performance enhancement. Examples are branch on constant, 16-bit push and pop stack, 16-bit logical, 16-bit bit mask and field extraction, shift followed ALU operations, and flow redirection for repeated code. On average, V3 architecture offers 20% program code size reduction over the V2 architecture on MCU applications. In addition, there are also optional saturation instructions for voice applications. On system architecture, V3 supports shadow stack pointer register to protect the contents of kernel stack pointer. In addition, V3 enhances the V2 vector interrupt architecture with priority-based preemption, including 4 priority levels and built-in interrupt controller for up to 32 interrupt sources. All-C Embedded Programming is another major benefit enabled by V3 architecture. Software engineers can program startup functions and ISRs (Interrupt Service Routines) in pure C language, and thereby gain higher productivity and reduce maintenance overhead. V3 makes major advancement for AndeStar while keeping full compatibility with V2.

V3m is the subset of V3 to enable smaller and lower power AndesCore™. V3m instructions are carefully selected from those most commonly used in MCU applications. In addition, V3m supports the priority-based preemption with built-in vector interrupt controller and All-C Embedded Programming.


The following lists the main features of AndeStar :

  • Intermixable 32-bit and 16-bit instruction sets without the need for mode switch
  • 16-bit instructions as a frequently used subset of 32-bit instructions
  • RISC-style register-based instruction set
  • 32 or 16 32-bit General Purpose Registers (GPR)
  • Upto 1024 User Special Registers (USR) for existing and extension instructions
  • Rich load/store instructions for
    • Single memory access with base address update
    • Multiple aligned and unaligned memory accesses for memory copy and stack operations
    • Data prefetch to improve data cache performance
    • Non-bus locking synchronization instructions
  • PC relative jump and PC read instructions for efficient position independent code
  • Multiply-add and multiple-sub capable of 64-bit result accumulation
  • Efficient power management through standby instruction and flexible interface signals
  • Bi-endian support
  • Optional coprocessor interface for
    • Andes-defined Floating-Point Coprocessor with efficient floating-point instructions
    • Customer coprocessor for customer-defined instruction extensions
  • Memory space management through :
    • 4-entry Non-translation cacheability and mapping table
    • Memory Protection Unit (MPU) for RTOS and bare-metal environment
    • Memory Management Unit for virtual memory OS with a choice of hardware or software page table walker
  • Memory hierarchy definition, including
    • Instruction and Data Local Memory (ILM and DLM): each occupying a relocatable part of the global address space
    • Instruction and Data Caches: the first level SW visible caches, capable of keeping contents in the global address space other than ILM/DLM