AndesCore™ Processors

AndesCore™ is made up of a series of high performance 32-bit/64-bit CPU core families specially designed to target different market segments of today’s emerging applications. The AndesCore™ processors are based on the AndeStar™ V5 instruction set architecture (ISA) and are compliant with RISC-V technology. According to the requirements of different targeted applications, the AndesCore™ processor supports the following CPU series:

Compact Series: 

N22 is an extremely streamlined, low-power and high-performance 32-bit 2-stage pipeline RISC-V CPU IP with performance of 3.95 Coremark/MHz and 1.8 DMIPS/MHz. D23 and N225 adopt 32-bit 3-stage pipeline RISC-V architecture for improved design, providing better performance, smaller code size and more security support. Both cores achieve industry-leading performance in their class, with outstanding benchmark scores such as 4.55 (D23)/4.4 (N225) Coremark/MHz, and 2.08 (D23)/1.92 (N225) DMIPS/MHz respectively.

25-Series: 

This series of CPUs are based on 32/64-bit 5-stage pipeline architecture. IP Models include N(X)25F, D25F, A(X)25, A(X)25MP, N25F-SE, and D25F-SE, which provide high per-MHz performance and high frequency operation with low gate count. The AX25MP symmetric multiprocessor supports up to 4 cores and a level-2 cache controller with instruction and data prefetch. Andes Coherence Unit (ACU) manages level-1 cache coherence, including I/O coherence for cacheless bus managers, and duplicated L1 tag to screen allocated lines for snoop queries.

27-Series: 

This series of CPUs are based on 32/64-bit 5-stage pipeline architecture, and IP Models include A(X)27, A(X)27L2, and NX27V. A(X)27L2 features branch prediction, level-1 instruction and data caches, level-2 unified cache, local memories, and other functions. In addition, it incorporates MemBoost to greatly enhance memory bandwidth and reduce memory latencies for applications with intensive memory accesses. NX27V includes a powerful vector processing unit (VPU). It is ideal for applications with large amounts of data, such as machine/deep learning, AR/VR, cryptography, multimedia processing, networking, and scientific computing.

40-Series: 

This series of CPUs are based on 32/64-bit dual-issue 8-stage pipeline architecture. IP Models include N(X)45, D45, A(X)45, A(X)45MP, and D45-SE. These issue two instructions per cycle and support MemBoost to significantly increase the performance efficiency. The AX45MPV symmetric multiprocessor supports up to eight cores and a level-2 cache controller with instruction and data prefetch. Coherence Manger ensures data coherence among CPU accesses and IO transactions from cacheless bus masters. The AX45MPV contains a powerful VPU with up to 1024-bit VLEN and DLEN and is excellent for computations involving large arrays of data such as computer vision, digital signal processing, image processing, machine/deep learning, and scientific computing.

60-Series: 

This series of CPUs are based on 64-bit out-of-order 4-wide 13-stage pipeline architecture. The AX65 symmetric multiprocessor supports up to eight cores and a level-2 cache controller with instruction and data prefetch. Coherence Manger ensures data coherence among CPU accesses and IO transactions from cacheless bus masters. Other features include ECC for level-1/2 memory soft error protection, Platform-Level Interrupt Controller (PLIC) with enhancements for vectored dispatch and priority-based preemption, and PowerBrake and WFI for power management.

The main functions supported by a CPU IP can be easily identified from its model name. The CPU model with N-prefix supports RTOS, A-prefix supports Linux, and D-prefix supports SIMD/DSP P-extension (draft), which was developed by Andes and contributed to the RISC-V Foundation. The CPU model marked with X is a 64-bit CPU core, otherwise it is a 32-bit CPU core. In more mature models MP-suffix denotes multi-core support, though in newer models like AX65 it is not called out explicitly. V-suffix indicates vector processing capability. CPU models marked with SE-suffix support functional safety.

Andes extends RISC-V with features including its own instructions to improve performance and functionality, such as Andes Custom Extension™ (ACE) to create instructions for customized acceleration, half precision floating point load/store instructions to accelerate high precision arithmetic processing. All cores are available in a reference design CPU subsystem with pre-integrated bus controller and peripheral components to facilitate SoC designs; and support features such as PowerBrake, QuickNap™, WFI for additional power saving, StackSafe™ for stack overflow/underflow protection, and CoDense™ for additional code density enhancement on top of RISC-V C-extension. 

The versatile and rich features of the AndesCore™ families allow flexible SoC customizations based on the application needs in a design to reduce system power/cost or improve platform performance. AndesCore™ products are available in the form of softcore to broadly satisfy the needs of processor IP sourcing and integration into an SoC. With innovative processor design techniques, the AndesCore™ CPU families provide better performance and power-efficiency superior to competing 32-bit/64-bit cores on the market. For low-power methodology implementation, AndesCore™ CPU further allows SoC-level power management to achieve better low-power designs through methods such as clock gating/power gating/AOPD (AlwaysOn power domain).