Learn the Latest on RISC-V and Vector Processing at All Six Andes Technology Corporation’s Presentations at the 2020 RISC-V Summit

SAN JOSE, CA – November 05, 2020 – Andes Technology Corporation (TWSE: 6533), a leading supplier of high efficiency, low-power 32/64-bit RISC-V processor cores and founding Premier member of RISC-V International will make six presentations at the virtual RISC-V Summit from December 8 to 10, 2020. 

Andes CTO and Executive VP, Charlie Hong-Men Su, will give an overview and update on “Andes RISC-V Processor IP Solutions.” Andes Senior Director of Architecture Div., Chuan-Hua Chang, will present “AndesClarity: a Performance & Bottleneck Analyzer for RISC-V Vector Processors.” Paul Ku, Deputy Technical Director of Architecture Div., will introduce “Building a Secure Platform with the Enhanced IOPMP.”

The SoC industry has seen fast-growing and diversified demands for a wide range of RISC-V based products: from tiny low-power MCUs for consumer devices, to chips powering enterprise-grade products and datacenter servers; from one power-efficient core to a thousand GHz+ cores working cohesively. Charlie Su will explain the rich portfolio of AndesCore™ RISC-V processor IPs already populating these SoCs: compact single-issue cacheless cores to feature-rich Linux-capable superscalar cores, cache-coherence multicores, and cores capable of processing floating-point and DSP data to those crunching a large volume of vector data. He will also update RISC-V IPs newly added to Andes processor portfolio, the associated software support and their performance data.

Additionally, Deputy Software Manager, Shao-Chung Wang, will present “Extending Multicore Programming Framework for Vector Extension.” Ding-Kai Huang, VLSI Manager, will discuss “Enhancing Verification Coverage for RISC-V Vector Extension Using RISCV-DV,” co-authored with Tao Liu from Google. Andes Principal Architect, Thang Tran, will hold a 3-hour master class entitled “RISC-V Vector Extension Demystified.”

For more information, please visit the RISC-V Summit website.

 

About Andes Technology Corp.
Andes Technology Corporation is a world class creator of innovative high-performance/low-power 32/64-bit processor cores and associated development environment that serves the rapidly growing global market for embedded system applications. As the founding Premier member of RISC-V International, Andes is the first mainstream CPU vendor that adopted the RISC-V as the base of its fifth-generation architecture, the AndeStar™ V5. To meet the demanding requirements of today’s electronic devices, Andes delivers highly configurable and performance-efficient CPU cores. They come with full-featured integrated development environment and comprehensive software/hardware solutions to help designers innovate their SoCs in a shorter time to market. In 2019, the volume of SoCs Embedded with Andes CPUs surpassed the 1.5-billion mark. Andes Technology’s comprehensive RISC-V CPU families range from the entry-level 32-bit N22, mid-range 32-bit N25F/D25F/A25/A27 and 64-bit NX25F/AX25/AX27, to the high-end multicore A(X)25MP and vector processor NX27V. Coming soon is the superscalar 45 series. For more information, please visit http://www.andestech.com/

Continue ReadingLearn the Latest on RISC-V and Vector Processing at All Six Andes Technology Corporation’s Presentations at the 2020 RISC-V Summit

Telink and Andes Announce the TLSR9 SoC with RISC-V Processor

SHANGHAI, CHINA – November 2, 2020 – Telink Semiconductor and Andes Technology are proud to introduce the new connectivity system on a chip (SoC) for Telink’s latest product line, the TLSR9 series. Powered by the Andes RISC-V core D25F, the TLSR9 series is designed for the next generation of hearables, wearables, and other high-performance IoT applications. Thanks to the companies’ partnership with IAR Systems, IoT designers will also have access to the powerful development toolchain IAR Embedded Workbench for flexible product development.

Enabling Innovative New IoT Products

The Telink TLSR9 series is the latest addition to Telink’s line of complete connectivity solutions, and it is designed to maximize device performance and minimize time to market. The TLSR9 series is designed using Andes’ latest AndeStar™ V5 Instruction Set Architecture (ISA), which is compliant to the RISC-V technology. As an open source instruction set architecture (ISA), RISC-V offers developers a great depth of design knowledge and facilitates more innovative and secure processor design.

The TLSR9 SoC features Andes 32-bit RISC-V processor D25F and is the world’s first SoC which adopts RISC-V DSP/SIMD P-extension that is ideal for a variety of mainstream audio, wearables and IoT development needs. The D25F has an efficient 5-stage pipeline and delivers the leading performance of 2.59 DMIPS/MHz and 3.54 CoreMark/MHz at its class. With RISC-V P-extension (RVP), it significantly increases the efficiency for small volume of data computation, and makes the compact AI/ML applications possible on the edge devices. It has been collected that 14.3x speedup of CIFAR-10 AI models, which is a typical image classification technology, and 8.9x speedup of keyword spotting technology, which consumed only dozens of million cycles per inference. Furthermore, the standard JTAG and Andes 2-wire serial debugging port helps to reduce the pin cost.

“We are excited to announce the news,” said Dr. Wenjun Sheng, CEO of Telink Semiconductor.“Telink has always been dedicated to building the future of the Internet of Things and consumer electronics. That means continuously exploring new ways to make chips that are at once more powerful and easier to put into action. By partnering with Andes Technology and IAR Systems to provide a top-notch processor and IDE for our new TLSR9 product line, we are committed to reducing the difficulty of application development and improving efficiency. Telink will continue to provide quick-to-market, performance enhanced, cost efficient solutions to our customers.”

“We believe the RVP is going to open a new era for data computation on MCU.” said Frankwell Lin, President of Andes Technology.“We are gratefully to cooperate with Telink and IAR to build the foundation of the RVP ecosystem for edge AIoT. With Telink TLSR9 and IAR EWRISC-V, developers can easily bring into full play the advantage of RVP. Andes contributed the first version of RVP specification to RISC-V last year, and it is at version 0.8 now. We are looking forward to ratification of RVP standard to enable more and more AIoT market for RISC-V with our partners.”

“We are happy to partner with Andes and Telink to deliver innovative new solutions for IoT developers,” says Kiyofumi Uemura, APAC Director, IAR Systems. “Together we have a lot to offer with regards to performance, and by providing maximized code speed and minimized code size for the TLSR9 series, we will create new possibilities to reduce time to market and ensure high quality applications.”

About Telink Semiconductor
Founded in 2010, Telink Semiconductor is a fabless integrated circuit design company with offices in Shanghai, Shenzhen, Taipei, Santa Clara, and London. Telink is dedicated to the development of highly integrated low-power radio frequency and mixed signal system chips for Internet of Things applications. Telink’s product portfolio is aimed at serving markets ranging from smart lighting to home automation to smart cities and currently includes 2.4GHz RF SoCs for Bluetooth, Zigbee, 6LoWPAN/Thread, and HomeKit. Visit Telink at http://www.telink-semi.com.

About Andes Technology
Fifteen years in business and a founding Premier member of RISC-V International, Andes Technology is a leading supplier of high-performance, low-power 32/64-bit embedded processor IP solutions and a major player in pushing RISC-V into the mainstream. Andes’ fifth-generation AndeStar™ architecture adopted the RISC-V as its base. Its V5 RISC-V CPU families range from tiny 32-bit cores to advanced 64-bit cores with DSP, FPU, Vector, Linux, dual-issue, and/or multi-core capabilities. Visit Andes at https://www.andestech.com

Continue ReadingTelink and Andes Announce the TLSR9 SoC with RISC-V Processor

瑞薩電子採用晶心RISC-V 32位元CPU核心開發其首款RISC-V架構ASSP產品

日本東京 – 2020年10月1日 – 全球半導體解決方案供應商瑞薩電子集團(TSE: 6723)宣佈與RISC-V架構嵌入式CPU核心及相關SoC開發環境的領先供應商晶心科技啟動技術IP合作。瑞薩選擇AndesCore™ IP 32位元RISC-V CPU核心IP，應用於其全新的專用標準產品中，並將於2021年下半年開始為客戶提供樣片。

晶心科技總經理林志明表示：「瑞薩作為頂級MCU供應商，已將晶心RISC-V核心設計到其預編程的專用標準產品中，對此我們感到十分榮幸。瑞薩和晶心有著相同的願景——迎接RISC-V成為SoC主流CPU指令集架構(ISA)的時代。雙方的合作不僅是晶心的里程碑，更標誌著開源RISC-V ISA即將成為主流計算引擎。瑞薩的客戶亦將受益於面向21世紀計算需求而構建的現代ISA。」

瑞薩電子執行副總裁、物聯網及基礎設施事業本部總經理Sailesh Chittipeddi表示：「晶心RISC-V核心IP提供的可擴展性能範圍、可選安全功能和訂製選項，使瑞薩能夠為未來針對特定應用的標準產品提供創新解決方案。幫助為現有或新興應用尋找經濟高效替代途徑的客戶，從更短的上市時間和更低的開發成本中獲益。」

瑞薩基於RISC-V核心架構的預編程ASSP元件，結合專用的用戶界面工具來設置應用的可編程參數，將為客戶構建完整且優化的解決方案。此功能消除了RISC-V開發初期及軟件投資相關的壁壘。此外，瑞薩廣泛的區域合作夥伴擁有豐富的專業知識，將為客戶提供前沿、專注的技術支持。

關於瑞薩電子集團
瑞薩電子集團 (TSE: 6723)，提供專業可信的創新嵌入式設計和完整的半導體解決方案，旨在通過使用其產品的數十億聯網智慧設備改善人們的工作和生活方式。作為全球領先的微控制器供應商、模擬功率元件和SoC產品的領導者，瑞薩電子為汽車、工業、家居、基礎設施及物聯網等各種應用提供綜合解決方案，期待與您攜手共創無限未來。更多資訊敬請至renesas.com。關注瑞薩電子微信公眾號及LinkedIn官方帳號，發現更多精彩內容。

Continue Reading瑞薩電子採用晶心RISC-V 32位元CPU核心開發其首款RISC-V架構ASSP產品