AndesCore™ N13 Overview

  • Optimized pipeline for best performance with over 1 GHz
  • Dynamic branch prediction accelerates loop execution
  • Unified Local Memory (ULM) for simultaneous accesses
  • 64-bit AXI bus for high bandwidth and low latency
  • MMU and MPU for Linux and RTOS
  • Support for FPU coprocessor and L2 cache

The Andes Technology N13 processor is a high performance CPU core architected for computation intensive applications running either on operating systems or as bare metal. The N13 is designed to serve the demanding requirements of application processors in SoCs for consumer electronics such as HDTVs, home media servers, cable and over-the-top set top boxes, as well as SoCs for the switches and routers delivering content to these devices.

Complete with Memory Management Unit, L1/L2 cache, Local Memory, DMA, FPU, Vectored Interrupt, and Branch Prediction, the N13 easily runs complex operating system such as Linux. And with an 8-stage pipeline and a clock rate over 1 GHz, the core delivers impressive performance of 2.05 DMIPS/MHz to serve the most demanding computing environments. Furthermore, the N13 AndesCore™ supports the latest AndeStar™ V3 architecture, which is accompanied with toolchain, IDE, RTOS, Linux, middleware, and platform development IP. The N13's strength plus its ecosystem provide designers with the competitive edge for success in their embedded system solutions.


  • Networking device
  • WiFi device
  • GPON
  • Surveillance system
  • ADAS
  • Storage device
  • Digital TV/Set top box
  • Media center

Block Diagram

Development Tools

  • AndeSight™ Integrated Development Environment
  • AICE JTAG/SDP debugger hardware

Key Features and Performance

AndeStar™ V3 Architecture
Key Features Benefits
21st-century RISC instruction set Better performance for modern compiler
16/32-bit mixable opcode format Smaller code size
Optional saturation instructions Efficient voice applications
32 general-purpose registers Better code size and performance
All-C Embedded Programming Faster SW development and easier maintenance
Shadow stack pointer Efficiency and protection with a dedicated kernel stack pointer
Hardware divider More performance
Aligned and unaligned load/store multiple word instructions Better program code size and performance
Direct support of up to 32 interrupts with programmable priority levels Quick identification of interrupt sources
Fast assignment of service routines
4G address space Full range address space
Memory mapped IO Friendliness to programmers and compilers
CPU Core
Key Features Benefits
2.05 DMIPS/MHz*
3.16 CoreMark/MHz*
Superior performance-per-MHz
8-stage pipeline High speed and high performance
Extensive branch predication (BTB and RAS) Better performance for branches
Hardware stack protection Stack size determination and runtime overflow error detection
Processor state bus Simplification of SoC design and debugging
Performance monitors Program code performance tuning
Memory Management Unit
  • 32/64/128-entry 4-way set-associative main TLB
  • Optional hardware page table walker
  • Support two groups of page size (4KB & 1MB, 8KB & 1MB)
  • Virtual memory support for full address space and easy code/data sharing
  • Support for full-featured OS such as Linux
  • Protection of superuser and user privilege
  • Hardware for fast address translation
Memory Protection Unit
  • 8 memory protection regions
Basic read/write/execute memory protection with minimum cost
Extensive clock gating and logic gating Lower power
N:1 core/bus clock ratios Simplified SoC integration
Low-latency vectored interrupt Faster context switch for real-time applications
Optional 64-bit data-path between bus and caches with power reduction architecture High bandwidth with lower latency
Efficient atomic access synchronization Non-bus locking mechanism
Coprocessor interface For Andes FPU and other customer designed coprocessor units

* BSP v4.2.0, DMIPS/MHZ without no-inline option, best performances

Memory Subsystems
Key Features Benefits
I & D Cache
  • Virtually Indexed and Physically Tagged (VIPT)
  • Size:8KB to 64KB, line size:16B/32B
  • Set associativity: Direct-mapped/2-way/4-way
Higher performance for large program size
  • Accelerating accesses to slow memories
  • Flexible cache configurations
  • VIPT for low power on context switch
Optional External Instruction and Data Local Memory
  • Size: 1KB to 4MB
  • ILM: program code, data and IO
  • DLM: program data
Higher efficiency for program execution
  • Flexible size selection to fit diversified needs
Optional unified local memory interface Flexible placement of code and data with minimal latency
Optional 2D local memory DMA Efficient data transfer
Error Correcting Code (ECC) for caches and local memory Code & data integrity protection
BIU supports 32-bit AHB/AHB-lite/APB and 32-bit/64-bit AXI User-selectable bus interface for optimal efficiency
Debug Support
Key Features Benefits
2-wire Serial Debug Port or 5-wire JTAG Debug Port Low-cost 2 wire support and industry-standard 5-wire support
Embedded Debug Module (EDM)
  • Up to 8 breakpoints and watchpoints
  • Secured debug access to system address space
  • Flexible configurations to trade off gate count and debugging capabilities
  • Code and data protection by allowing only authorized debugging
Process 40LP 28HPM
Max frequency (MHz) 986 >1500
Dynamic power (uW/MHz) 46.4 32.0
Area (mm2) 0.19 0.09

* Base configuration, LVT library; Frequency at slow process corner, 0.81V, 125°C and without I/O constraint; Power consumption at typical process corner, 0.9V, 25°C